Avalanche programmed floating gate memory cell structure with program element in polysilicon

A non-volatile memory cell structure, comprising:

• a semiconductor substrate having a surface and a doping concentration of a first conductivity type;
• a first oxide layer on the surface of the substrate;
• a floating gate constructed in a first polysilicon layer on a first portion of the first oxide layer and overlying a first portion of the surface of the substrate;
• a second oxide layer on the floating gate;
• a control gate formed in a first portion of a second polysilicon layer operatively coupled to a first portion of the floating gate;
• an injection element including a p/n junction formed in a second portion of the second polysilicon layer;
• and
• a sense transistor including a first source region, and a first drain region both formed in the substrate, and a portion of the floating gate separated from the first source region and the first drain region by a second portion of said first oxide layer.

An EEPROM structure, comprising:

• a semiconductor substrate of a first conductivity type having a surface;
• a sense transistor including a first source and drain regions formed in the substrate adjacent to the surface of said substrate;
• a floating gate positioned adjacent to the surface of the substrate and separated from said surface by a gate oxide layer, the floating gate having a first portion overlying the first transistor and at least a second portion overlying a device isolation region;
• an injection element in a polysilicon layer overlying the floating gate and separated from it by an oxide layer;
• wherein the injection element is constructed so that a reverse voltage breakdown condition generated in the element adds or removes electrons from the floating gate when an appropriate voltage is applied to the floating gate.

A memory array comprising a plurality of memory cells on a semiconductor substrate, comprising:

• a plurality array control gate voltage conductors;
• a plurality of write bit line conductors;
• a plurality of product term gates;
• a plurality of word lines;
• a plurality of product terms;
• an array of memory cells, each cell comprising:
• a floating gate formed in a first polysilicon layer coupled to one of said array control gate conductors;
• an array control gate formed in a second polysilicon layer overlying the first polysilicon layer and coupled to one of the plurality of array control gate voltage conductors;
• a reverse breakdown electron injection element at least partially formed in said second polysilicon layer and operatively coupled to the floating gate, having a first active region coupled to one of said plurality or write bit line conductors and a second active region coupled to one of said plurality of write word lines, the regions forming a PN junction;
• a sense transistor comprising a source, drain and channel regions formed in the substrate, and underlying a portion of the floating gate;
• and
• a read transistor at least partially formed in the semiconductor substrate sharing said source of said sense transistor as a drain region and having a source region, and including a control gate coupled to one of said word line conductors.