Integrated circuit structure comprising capacitor element and corresponding manufacturing process
AssigneeSTMicroelectronics S.r.l.
InventorRaffaele Zambrano
Life of this patent
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Abstract
A circuit structure for semiconductor devices which are integrated on a semiconductor layer is provided. The structure comprises at least one MOS device and at least one capacitor element that has a bottom and a top electrode. The MOS device has conduction terminals formed in the semiconductor layer, as well as a control terminal covered with an overlying insulating layer of unreflowed oxide. The capacitor element is formed on the unreflowed oxide layer.
Claims20
A circuit structure integrated on a semiconductor substrate comprising:
- a MOS device;
- a capacitor element;
- said MOS device having conduction terminals formed in the semiconductor layer and a control terminal covered with an overlying insulating layer whereon said capacitor element is formed;
- said capacitor element having a bottom electrode and a top electrode;
- wherein said overlying insulating layer is an unreflowed oxide;
- and
- contacts formed at openings provided in the insulating layer, the openings having surface edges, walls, and bottoms coated with a layer of a conducting material and filled with an insulating fill layer.
A circuit structure integrated on a semiconductor substrate comprising:
- a MOS device having conduction terminals formed in the semiconductor substrate and a control terminal covered with an overlying insulating layer, said overlying insulating layer formed of an unreflowed oxide;
- contacts formed at openings provided in said overlying insulating layer between said conduction terminals and a surface of said overlying insulating layer at an offset portion of said overlying insulating layer which is laterally offset relative to the conduction terminals of said MOS device, said openings each having an edge, a wall, and a bottom coated with a layer of a conducting material and filled with an insulating fill layer;
- and
- a capacitor element having a bottom electrode and a top electrode, one of said bottom electrode and said top electrode formed on an offset portion of one of said contacts formed over said offset portion of said overlying insulating layer.
A circuit structure integrated on a semiconductor substrate comprising:
- a MOS device;
- a capacitor element having a bottom electrode and a top electrode;
- said MOS device having conduction terminals formed in the semiconductor substrate and a control terminal covered with an overlying insulating layer whereon said capacitor element is formed;
- and
- contacts formed at openings provided in said overlying insulating layer between a surface of said overlying insulating layer and said conduction terminals, said openings having surfaces coated with a layer of a conducting material and filled with an insulating fill layer.
Dependencies are inferred from the claim text.