Method to improve TiSix salicide formation

A method for manufacturing titanium silicide regions for electrical contact to a semiconductor device, comprising the sequential steps of:

• providing a silicon semiconductor substrate having a surface whereby said substrate has been provided with a semiconductor device whereby said semiconductor device is a partially completed gate electrode structure;
• depositing a layer of Resist Protection Oxide (RPO) over a surface of said substrate thereby including a surface of said partially completed gate electrode;
• patterning and etching said layer of RPO thereby creating openings in said layer of RPO whereby said openings overlay and expose said regions where salicided regions need to be formed whereby said etch is an time-mode etch;
• performing an impurity implant of arsenic (As) or boron (BF2) into said surface of said substrate thereby including said exposed surfaces of said regions where salicided regions have to be created;
• performing a pre-metal wet dip of said substrate;
• depositing a layer of titanium over said surface of said substrate thereby including said regions where titanium silicide regions have to be created;
• performing a silicon ion mixing implant into said surface of said substrate thereby including said regions where titanium silicide regions have to be created;
• performing a first Rapid Thermal Anneal of said surface of said substrate thereby forming reacted and unreacted titanium on said surface of said substrate;
• removing said unreacted titanium from said surface of said substrate;
• and
• performing a second Rapid Thermal Anneal of said surface of said substrate.

A method of forming a layer of TiSix over a silicon surface, comprising the steps of:

• providing a silicon surface whereby said silicon surface typically is but is not limited to a surface of a semiconductor substrate;
• implanting a p-type impurity into said silicon surface;
• implanting an n-type impurity into said silicon surface whereby said n-type implant is adjacent to said p-type implant whereby however said n-type implant is not necessarily immediately contiguous with said p-type implant;
• performing a As or BF2 implant into said silicon surface;
• depositing a layer of refractory metal over said silicon surface;
• performing a silicon ion implant into a surface of said layer of refractory metal;
• performing a first thermal anneal of said layer of refractory metal thereby creating reacted and unreacted titanium;
• removing said unreacted titanium from said silicon surface;
• and performing a second thermal anneal of said layer of refractory metal thereby transforming said reacted titanium from a high resistivity phase to a low resistivity phase.