Method for fabrication of enlarged stacked capacitors using isotropic etching

A method for forming stacked capacitors for a semiconductor memory device comprising the steps of:

• providing a substrate having a planarized dielectric layer formed on access transistors, the planarized dielectric layer having conductive plugs disposed therein for connecting to the access transistors;
• forming a first dielectric layer on a top surface of the planarized dielectric layer;
• forming a second dielectric layer which is selectively etchable relative to the first dielectric layer;
• patterning holes in the second dielectric layer by selectively etching the second dielectric layer relative to the first dielectric layer;
• and
• isotropically etching the holes in the second dielectric layer to expand the holes to provide an increased surface area within the holes over a surface area formed by the selectively etching the second dielectric layer.

A method for forming stacked capacitors for a dynamic random access memory device comprising the steps of:

• providing a substrate having a planarized glass layer formed on access transistors, the planarized glass layer having conductive plugs disposed therein for connecting to the access transistors;
• forming a nitride layer on a top surface of the planarized glass layer;
• forming an oxide layer which is selectively etchable relative to the nitride layer;
• depositing a resist layer on the oxide layer;
• patterning the resist layer by forming openings in the resist over locations for the conductive plugs;
• anisotropically etching holes in the oxide layer by selectively etching the oxide layer relative to the nitride layer;
• isotropically etching the holes in the oxide layer to expand the holes to provide an increased surface area within the holes over a surface area formed by the selectively etching the oxide layer;
• removing the resist layer;
• removing portions of the nitride layer in the holes to expose the conductive plugs;
• depositing a conductive layer in the holes to form a bottom electrode for the stacked capacitors;
• and
• depositing a capacitor dielectric layer on the conductive layer.