Method of reducing word line resistance and contact resistance
AssigneeVanguard International Semiconductor Corporation
InventorsHuey-Chi Chu, Jia-Ching Doong, Chung-Pin Yang
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Abstract
By introducing a carefully controlled anneal step after the deposition of tungsten silicide (onto a layer of polysilicon) but before the deposition of a layer of silicon oxide, interaction between the tungsten silicide and a subsequently deposited layer of silicon oxide is greatly reduced or eliminated. This gives good values for the resistance of gate lines formed from the composite as well as for the contact resistance between the polysilicon and the tungsten silicide.
Claims12
A method to reduce contact and line resistance, comprising the sequential steps of:
- depositing a layer of polysilicon;
- depositing a layer of tungsten silicide by sputtering;
- annealing at a temperature between about 750 and 800° C. for between about 50 and 70 minutes;
- depositing a layer of silicon oxide;
- and
- patterning and etching said layers whereby a tungsten silicide line in contact with a polysilicon gate pedestal is formed.
A process for reducing resistance and contact resistance of a word line in a DRAM structure, comprising the sequential steps of:
- providing a p-type silicon substrate;
- forming a layer of gate oxide on said silicon substrate;
- depositing a layer of polysilicon on said layer of gate oxide;
- by sputtering, depositing a layer of tungsten silicide on said layer of polysilicon;
- annealing at a temperature between about 750 and 800° C. for between about 50 and 70 minutes;
- depositing a layer of silicon oxide over the layer of tungsten silicide;
- patterning and etching said layers whereby a gate line and a gate pedestal having vertical sidewalls are formed;
- implanting donor ions into the silicon substrate using said gate pedestal as a mask, to a first depth and to a first implanted ion concentration;
- forming insulating spacers on said vertical sidewalls of the gate;
- and
- using said gate, including the spacers, as a mask, implanting donor ions into the silicon substrate to a second depth, greater than said first depth, and to a second implanted ion concentration, greater than said first concentration, thereby forming a lightly doped drain structure having low contact resistance between said gate line and said gate pedestal.
Dependencies are inferred from the claim text.