Non-volatile semiconductor memory device and fabrication method thereof
AssigneeSeiko Epson Corporation
InventorsTomoyuki Furuhata, Koji Kato
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Abstract
A non-volatile semiconductor memory device is provided with a circuit that protects a tunnel oxide film from the charging phenomenon. This circuit comprises a first junction diode including an N+-type diffusion layer and a P-type well, and a second junction diode including a P-type well and an N-type well. When a voltage applied to the control gate is greater than all of a write voltage, a read voltage, and an erasure voltage that would be applied to the control gate, a current is guided through that circuit.
Claims6
A method of fabricating a non-volatile semiconductor memory device comprising a semiconductor substrate and a memory element provided with a floating gate and a control gate, said method including steps of:
- forming a first well in said semiconductor substrate;
- forming a second well within said first well, said second well having a conductivity opposite to that of said first well;
- forming a tunnel insulation film on said semiconductor substrate;
- forming a floating gate on said tunnel insulation film;
- forming a dielectric film so as to cover said floating gate;
- selectively removing said dielectric film to form a contact hole through which said second well is exposed;
- forming a conductive film that will become said control gate on said dielectric film, in such a manner as to be in contact with said second well through said contact hole;
- and
- thermally processing said conductive film to diffuse impurities contained within said conductive film into said second well to form a first conductive layer.
A method of fabricating a non-volatile semiconductor memory device comprising a semiconductor substrate and a memory element provided with a floating gate and a control gate, said method including steps of:
- forming a first well in said semiconductor substrate;
- forming a second well within said first well, said second well having a conductivity opposite to that of said first well;
- forming a tunnel insulation film on said semiconductor substrate;
- forming a floating gate, a dielectric film, and a control gate in sequence above said semiconductor substrate;
- forming a first conductive layer in said second well;
- forming an interlayer dielectric film above said semiconductor substrate so as to cover said control gate and said first conductive layer;
- selectively removing said interlayer dielectric film to form a first contact hole through which said control gate is exposed, and a second contact hole through which said first conductive layer is exposed;
- and
- forming a wiring layer on said interlayer dielectric film, which is electrically connected to both of said control gate and said first conductive layer through said first and second contact holes.
Dependencies are inferred from the claim text.