Drop-in test structure and abbreviated integrated circuit process flow for characterizing production integrated circuit process flow, topography, and equipment

Abstract

A drop-in test structure fabricated upon a virtual integrated circuit elevational profile and a method for using the drop-in test structure for characterizing an integrated circuit production methodology and integrated circuit fabrication equipment are described. According to an embodiment, the test structure may be fabricated upon an elevational profile corresponding elevationally to a complete or substantially complete production integrated circuit topography. According to an alternative embodiment, the test structure may be fabricated upon an elevational profile corresponding elevationally to a partially complete production topography. The test structure and method may be used to characterize the underlying elevational profile and to identify both systematic and random defects either as part of routine monitoring or in response to the observance of defective chips using other monitoring. The test structure and method may also be used to characterize the effects of intentional modifications to existing processing parameters and equipment and to characterize the performance of new processes and equipment.

Dependencies are inferred from the claim text.