Process to achieve uniform groove depth in a silicon substrate

A method of fabricating a grooved gate, metal oxide semiconductor field effect transistor, (MOSFET), device, on a semiconductor substrate, comprising the steps of:

• depositing an insulator layer on said semiconductor substrate;
• patterning of said insulator layer to form an insulator mask, with an opening in said insulator mask, exposing a portion of said semiconductor substrate;
• performing a selective, anisotropic RIE procedure, creating a groove in the region of said semiconductor exposed in said opening, in said insulator mask, with the depth of said groove finalized when complete removal of said insulator mask is accomplished, during said selective, anisotropic RIE procedure, wherein said selective, anisotropic RIE procedure, used to form said groove, is performed using an etchant chosen from a group that includes Cl2/HBr/He—O2, SF6/O2, or CF4/O2, with an etch rate ratio of silicon to silicon oxide, between about 40 to 1, to 1, and wherein said groove is formed to a depth between about 800 to 1500 Angstroms, and with a width between about 300 to 1300 Angstroms;
• growing a silicon oxide, gate insulator layer,
• depositing a polysilicon layer;
• patterning of said polysilicon layer to form a grooved gate, polysilicon structure, with a first portion of said grooved gate, polysilicon structure, located in said groove, and with a second portion of said grooved gate, polysilicon structure, overlying a portion of the top surface of said semiconductor substrate, in a region adjacent to said groove;
• forming a source/drain region in an area of said semiconductor substrate, not occupied by said grooved gate, polysilicon gate structure;
• forming insulator spacers on the sides of said second portion of said grooved gate, polysilicon structure;
• and
• forming a heavily doped, source/drain region in an area of said semiconductor substrate, not covered by said grooved gate, polysilicon structure, or by said insulator spacers.