Back to results
US 6,274,494 B1Granted
Method of protecting gate oxide
AssigneeUnited Microelectronics Corp.
InventorsMu-Chun Wang, Yih-Jau Chang
Life of this patent
Estimating the term…
Abstract
A method of protecting gate oxide. A chip having a gate thereon is provided. The gate structure comprises a gate oxide layer and a gate electrode. The gate is covered by a dielectric layer. A protection layer is formed on the dielectric layer. The protection layer is pattern to remain a part of the protection layer aligned over the gate.
Claims16
A method of protecting gate oxide, comprising:
- providing a substrate having a gate thereon;
- forming a dielectric layer on the substrate and the gate;
- forming a patterned protection layer on the dielectric layer, the patterned protection layer being aligned over both sides of the gate.
A method of protecting gate oxide, comprising:
- providing a substrate having a gate thereon;
- forming a dielectric layer on the substrate and the gate;
- and
- forming a protection layer on the dielectric layer aligned over both sides of the gate, wherein the protection layer comprises a conductive layer.
1 more element
A method of protecting gate oxide, comprising:
- providing a substrate having a gate thereon;
- forming a dielectric layer on the substrate and the gate;
- and
- forming a protection layer on the dielectric layer aligned over both sides of the gate, wherein the protection layer comprises a tungsten layer.
1 more element
A method of protecting gate oxide, comprising:
- providing a substrate;
- forming a gate oxide layer on the substrate;
- forming a gate electrode on the gate oxide layer;
- forming a dielectric layer on the gate electrode and the substrate;
- forming a first protection layer on the dielectric layer;
- patterning the first protection layer, the patterned first protection layer being aligned over both sides of the gate electrode;
- forming an inter-metal dielectric layer on the patterned first protection layer and the dielectric layer;
- and
- forming a second protection layer on the inter-metal dielectric layer being aligned over the first protection layer.
6 more elements
A fabrication method for a multi-level interconnect, comprising:
- forming a gate on a substrate;
- forming a first dielectric layer on the gate and the substrate;
- forming a first protection layer on the dielectric layer, wherein the first protection layer aligned over both sides of the gate;
- forming a second dielectric layer on the first protection layer and on the first dielectric layer;
- f forming a metal layer on the second dielectric layer;
- forming a third dielectric layer on the metal layer;
- and
- forming a second protection layer on the third dielectric layer, wherein the second protection layer aligned over the first protection layer.
5 more elements
Dependencies are inferred from the claim text.