High performance MIM (MIP) IC capacitor process

A method for fabricating a capacitor comprising:

• providing an insulating layer overlying a semiconductor substrate;
• forming a capacitor bottom plate electrode and an interconnection line overlying said insulating layer wherein a gap is formed between said bottom plate electrode and said interconnection line;
• depositing a capacitor dielectric layer overlying said capacitor bottom plate electrode and said interconnection line;
• depositing an etch stop layer overlying said capacitor dielectric layer;
• coating said etch stop layer with a spin-on-glass material layer wherein said gap is filled by said spin-on-glass material;
• planarizing said spin-on-glass material layer whereby said spin-on-glass material is left only within said gap;
• depositing an oxide layer overlying said planarized spin-on-glass layer;
• etching away said oxide layer over said capacitor bottom plate electrode stopping at said etch stop layer whereby a recess is formed in said oxide layer overlying said bottom plate electrode wherein sidewalls of said oxide layer overlie the edges of said bottom plate electrode;
• forming a first via opening through said oxide layer, said etch stop layer, and said capacitor dielectric layer to said interconnection line;
• depositing a first metal layer overlying said substrate and filling said first via opening and said recess;
• patterning said first metal layer to form a metal line contacting said interconnection line through said first via opening, to form a capacitor top plate electrode within said recess and to form a guard ring on said sidewalls of said oxide layer within said recess wherein gaps are left between said capacitor top plate electrode and said guard ring;
• and
• covering said patterned first metal layer over said interconnection line and said top plate electrode with a dielectric layer wherein said gaps are filled by said dielectric layer to complete formation of said capacitor in the fabrication of said integrated circuit device.