Non-volatile memory structure and corresponding manufacturing process

A semiconductor non-volatile memory device comprising:

• a plurality of memory cells each including a floating gate transistor having an active area, source and drain regions, a floating gate, and a control gate, a contact to the control gate being located above a field oxide region and not above the active area;
• and
• a plurality of selection transistors, each of the floating gate transistors being serially coupled to one of the selection transistors,
• wherein each memory cell is coupled to a bit line that is formed by at least a second metal interconnection layer, the bit line being electrically connected to the drain region, and
• the electrical connection of the bit line to the drain region is realized by a stacked contact that is active to a first metal interconnection layer and another contact between the first metal interconnection layer and the second metal interconnection layer.

A semiconductor non-volatile memory device comprising:

• at least one memory cell including a floating gate transistor that has an active area source and drain regions, a floating gate, and a control gate;
• at least one selection transistor serially coupled to the floating gate transistor;
• a control gate line formed by at least a first metal interconnection layer, the control gate line being electrically connected to the control gate of the memory cell by a contact that is located above the active area;
• and
• a bit line formed by at least a second metal interconnection layer, the bit line being electrically connected to the drain region,
• wherein the electrical connection of the bit line to the drain region is realized by a stacked contact that is active to the first metal interconnection layer and another contact between the first metal interconnection layer and the second metal interconnection layer.

An information handling system including at least one semiconductor non-volatile memory device, said memory device comprising:

• a plurality of memory cells each including a floating gate transistor having an active area, source and drain regions, a floating gate, and a control gate, a contact to the control gate being located above the active area;
• and
• a plurality of selection transistors, each of the floating gate transistors being serially coupled to one of the selection transistors,
• wherein each memory, cell is coupled to a bit line that is formed by at least a second metal interconnection layer, the bit line being electrically connected to the drain region, and
• the electrical connection of the bit line to the drain region is realized by a stacked contact that is active to a first metal interconnection layer and another contact between the first metal interconnection layer and the second metal interconnection layer.