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US 6,204,136 B1Granted
Post-spacer etch surface treatment for improved silicide formation
AssigneeAdvanced Micro Devices, Inc.
InventorsSimon S. Chan, Minh Van Ngo, Paul R. Besser, Angela T. Hui
Life of this patent
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Abstract
Sub-micron dimensioned, ultra-shallow junction MOS and/or CMOS transistor devices having reduced or minimal junction leakage are formed by a salicide process wherein carbonaceous residue on silicon substrate surfaces resulting from reactive plasma etching for sidewall spacer formation is removed prior to salicide processing. Embodiments include removing carbonaceous residues by performing a hydrogen ion plasma treatment.
Claims20
A method of manufacturing a semiconductor device, which method comprises the sequential steps of:
- (a) providing a semiconductor substrate having a surface;
- (b) forming a thin gate insulator layer in contact with said substrate surface;
- (c) forming a gate electrode on a portion of said gate insulator layer, said gate electrode comprising first and second opposing side surfaces and a top surface;
- (d) forming a blanket layer of an insulative material on the exposed portions of said thin gate insulator layer on said substrate surface and on said first and second opposing side surfaces and said top surface of said gate electrode;
- (e) selectively removing, by anisotropically etching, (1) said blanket layer of insulative material and underlying portions of said thin gate insulator layer from said substrate surface, and (2) said blanket layer of insulative material from said top surface of said gate electrode, thereby forming am insulative sidewall spacer on each of said first and second opposing side surfaces of said gate electrode and exposing portions of said substrate surface adjacent said sidewall spacers;
- and
- (f) removing residue and/or contaminants resulting from said anisotropically etching from at least said exposed portions of substrate surface adjacent said sidewall spacers.
4 more elements
A method of manufacturing an MOS semiconductor device, which method comprises the sequential steps of:
- (a) providing a silicon semiconductor substrate having a surface;
- (b) forming a thin silicon oxide gate insulator layer in contact with said substrate surface;
- (c) forming a gate electrode comprising heavily-doped polysilicon on a portion of said gate insulator layer, said gate electrode comprising first and second opposing side surfaces and a top surface;
- (d) forming a blanket layer of an insulative material comprising an oxide, nitride, or an oxynitride of silicon on the exposed portions of said thin gate insulator layer on said substrate surface and on said first and second opposing side surfaces and said top surface of said gate electrode;
- (e) selectively removing, by anisotropically etching, (1) said blanket layer of insulative material and underlying portions of said gate insulator layer from said substrate surface, and (2) said blanket layer of insulative material from said top surface of said gate electrode, thereby forming an insulative sidewall spacer on each of said first and second opposing side surfaces and exposing portions of said substrate surface adjacent said sidewall spacers;
- (f) removing residue and/or contaminants resulting from said anisotropically etching from at least said exposed portions of said substrate surface adjacent said sidewall spacers;
- (g) forming a blanket layer of a metal in contact with said exposed portions of said substrate surface adjacent said sidewall spacers, said top surface of said gate electrode, and said insulative sidewall spacers;
- (h) reacting said blanket metal layer to selectively form an electrically conductive silicide of said metal at portions thereof in contact with said exposed portions of said silicon substrate surface adjacent said sidewall spacers and said top surface of said polysilicon gate electrode;
- and
- (i) selectively removing unreacted portions of said blanket metal layer in contact with said insulative sidewall spacers.
7 more elements
Dependencies are inferred from the claim text.