Method of fabricating a mask ROM
AssigneeWorldwide Semiconductor Manufacturing Corp.
InventorLing-Sung Wang
Life of this patent
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Abstract
A method of fabricating a mask read-only memory. Before carrying out a code implantation, a coding mask is used as an etching mask to remove a portion of the inter-metal dielectric layer and the inter-layer dielectric layer above the coding positions, thereby forming a contact window. The code implantation is subsequently carried out so these ions can easily reach the coding positions via the contact opening.
Claims13
A method of fabricating a mask read-only memory (mask ROM) for forming a circuit having a mask ROM and other types of memory or logic devices therein, comprising the steps of:
- providing a substrate having a plurality of bit lines, a plurality of word lines, an inter-layer dielectric layer, an inter-metal dielectric layer and a metallic interconnect pattern;
- performing a photolithographic operation to form a coding mask for code implantation over the inter-metal dielectric layer;
- etching the inter-metal dielectric layer and the inter-layer dielectric layer to form a contact opening leading to a device using the coding mask as an etching mask;
- performing an ion implantation to implant ions into coding positions of the substrate of the device;
- removing the coding mask;
- and
- depositing dielectric material to form a dielectric layer inside the contact opening.
A method of fabricating mask read-only memory (mask ROM) for forming a circuit having a mask ROM and other types of memory or logic devices therein, comprising the steps of:
- providing a substrate;
- forming a buried bit line in the substrate;
- forming a gate dielectric layer over the substrate;
- forming a word line over the gate dielectric layer;
- forming an inter-layer dielectric layer over the word line and the gate dielectric layer;
- forming a conductive plug in the inter-layer dielectric layer such that the conductive plug is electrically connected to the buried bit line in the substrate;
- forming a metallic interconnect pattern over the inter-layer dielectric layer;
- forming an inter-metal dielectric layer over the metallic interconnect pattern and the inter-layer dielectric layer;
- performing a photolithographic operation to form a coding mask for code implantation over the inter-layer dielectric layer;
- etching the inter-metal dielectric layer and the inter-layer dielectric layer to form a contact opening using the coding mask as an etching mask;
- performing an ion implantation to implant ions into coding positions of the substrate of the device;
- removing the coding mask;
- and
- depositing dielectric material to form a dielectric layer inside the contact opening.
A method of fabricating a mask read-only memory (mask ROM) for forming a circuit having a mask ROM and dynamic random access memory (DRAM) therein, comprising the steps of:
- providing a substrate;
- forming a buried bit line in the substrate;
- forming a gate dielectric layer over the substrate;
- forming a word line over the gate dielectric layer;
- forming an inter-layer dielectric layer over the word line and the gate dielectric layer;
- planarizing the inter-layer dielectric layer;
- forming a conductive plug in the inter-layer dielectric layer such that the conductive plug is electrically connected to buried bit line in the substrate;
- forming a metallic interconnect pattern over the inter-layer dielectric layer;
- forming an inter-metal dielectric layer over the metallic interconnect pattern and the inter-layer dielectric layer;
- planarizing the inter-metal dielectric layer;
- performing a photolithographic operation to form a coding mask for code implantation over the inter-metal dielectric layer;
- etching the inter-metal dielectric layer and the inter-layer dielectric layer to form a contact opening using the coding mask as an etching mask;
- performing an ion implantation to implant ions into coding positions of the substrate of the device;
- removing the coding mask;
- depositing dielectric material to form a dielectric layer inside the contact opening;
- and
- planarizing the dielectric layer.
Dependencies are inferred from the claim text.