Method to fabricate a flash memory cell with a planar stacked gate

A method of fabricating a Flash EEPROM device comprising:

• providing isolation regions on and in a semiconductor substrate to separate active device regions from one another;
• providing a tunneling oxide layer on the surface of said semiconductor substrate;
• depositing a first polysilicon layer overlying said tunneling oxide layer, said isolation regions and said semiconductor substrate;
• thereafter polishing away said first polysilicon layer until the top surface of said first polysilicon is flat and parallel to the top surface of said semiconductor substrate but not exposing any of said underlying isolation regions and said underlying tunneling oxide layer;
• thereafter etching away said first polysilicon layer to form a floating gate in areas defined by photolithographic process;
• forming source and drain regions within said semiconductor substrate associated with said floating gate;
• depositing an interpoly dielectric layer overlying said floating gate;
• depositing a second polysilicon layer overlying said interpoly dielectric layer;
• etching away said second polysilicon layer and said interpoly dielectric layer in areas defined by photolithographic process to form a control gate overlying said floating gate;
• depositing an insulating layer overlying said control gate;
• forming contact openings through said insulating layer to said underlying control gate and to said underlying source and drain regions;
• and
• filling said contact openings with a conducting layer to complete said fabrication of said Flash EEPROM device.

A method of fabricating a Flash EEPROM device comprising:

• providing local oxidation of silicon (LOCOS) isolation regions in and on a semiconductor substrate to separate active device regions from one another;
• providing a tunneling oxide layer on the surface of said semiconductor substrate;
• depositing a first polysilicon layer overlying said tunneling oxide layer, said isolation regions and said semiconductor substrate;
• thereafter polishing away said first polysilicon layer until the top surface of said first polysilicon layer is flat and parallel to the top surface of said semiconductor substrate but not exposing any of said underlying isolation regions and said underlying tunneling oxide layer wherein 30 to 60% of said polysilicon layer is polished away;
• thereafter etching away said first polysilicon layer to form a floating gate in areas defined by photolithographic processes;
• forming source and drain regions within said semiconductor substrate associated with said floating gate;
• depositing an interpoly dielectric layer overlying said floating gate;
• depositing a second polysilicon layer overlying said interpoly dielectric layer;
• etching away said second polysilicon layer and said interpoly dielectric layer in areas defined by photolithographic processes to form a control gate overlying said floating gate;
• depositing an insulating layer overlying said control gate;
• forming contact openings through said insulating layer to said underlying control gate and to said underlying source and drain regions;
• and
• filling said contact openings with a conducting layer to complete said fabrication of said Flash EEPROM device.