Screened EEPROM cell
AssigneeSTMicroelectronics S.r.l.
InventorsFederico Pio, Nicola Zatelli, Laurent Sourgen, Mathieu Lisart
Life of this patent
Estimating the term…
Abstract
An EEPROM cell is described as having a screening metal structure formed of preference in the first metal layer and located in substantial overlaying relationship at the floating gate terminal. This defeats the possibility of anomalous readings being obtained by measuring the amount of charge on the floating gate terminal. An additional screening metal structure, to be formed in the third and following metal layers, may be provided to fully overlie the cell and provide additional protection against anomalous readings.
Claims16
An EEPROM memory cell, comprising:
- a floating gate transistor formed on a semiconductor substrate with a floating gate terminal;
- a first selection transistor coupled to the floating gate transistor and having a polysilicon selection terminal;
- a first metal layer positioned above the semiconductor substrate;
- and
- a second metal layer positioned further from the substrate than the first metal layer, wherein the first metal layer includes a screening first metal structure arranged to substantially overlie the floating gate terminal and wherein the first metal layer further includes a second metal structure that directly contacts the selection terminal in an overlapped relationship.
An EEPROM memory cell, comprising:
- a semiconductor substrate;
- a floating gate transistor formed on the semiconductor substrate;
- a first selection transistor coupled to the floating gate transistor and having a polysilicon selection terminal;
- a first metal structure substantially covering the floating gate transistor;
- a second metal structure overlapping the first metal structure;
- and
- a third metal structure directly contacting the selection terminal in an overlapping relationship.
Dependencies are inferred from the claim text.