Methods of forming SOI insulator layers, methods of forming transistor devices, and semiconductor devices and assemblies

A semiconductor processing method of forming a thin film transistor comprising:

• providing a substrate;
• defining a source template portion, a channel template portion and a drain template portion of the substrate;
• doping the source and drain template portions differently than the channel template portion;
• forming an insulator layer over the substrate;
• forming a semiconductive layer over the insulator layer;
• forming a depletion region within the semiconductive layer, the depletion region being over the source template portion, the channel template portion and the drain template portion, the depletion region being proximate the insulator layer and being thinner over the channel template portion than over the source and drain template portions;
• while the depletion region is formed, exposing the semiconductive layer to an electrolytic etching composition to etch the semiconductive layer to about the depletion region, the etched semiconductive layer being thinner over the channel template portion than over the source and drain template portions, the etched semiconductive layer over the channel template portion comprising a transistor channel, the etched semiconductive layer over the source template portion comprising a transistor source, and the etched semiconductive layer over the drain template portion comprising a transistor drain;
• forming a transistor gate proximate the channel;
• and
• incorporating the transistor source, transistor drain, transistor channel and transistor gate into a thin film transistor.

A semiconductor processing method of forming p-channel and n-channel devices comprising:

• providing a substrate;
• defining p-channel and n-channel template portions of the substrate;
• forming an insulator layer over the substrate;
• forming a semiconductive layer over the insulator layer;
• forming a depletion region within the semiconductive layer, the depletion region being over the n-channel template portion and over the p-channel template portion, the depletion region being proximate the insulator layer and having a different thickness over the p-channel template portion than over the n-channel template portion;
• while the depletion region is formed, exposing the semiconductive layer to an electrolytic etching composition to etch the semiconductive layer to about the depletion region, the etched semiconductive layer comprising a different thickness over the p-channel template portion than over the n-channel template portion;
• forming a p-channel transistor from the etched semiconductive layer over the p-channel template portion;
• and
• forming an n-channel transistor from the etched semiconductive layer over the n-channel template portion.

A semiconductor processing method of forming peripheral transistor devices and memory array transistor devices comprising:

• providing a substrate;
• defining peripheral transistor device template portions and memory array transistor device template portions of the substrate;
• forming an insulator layer over the substrate;
• forming a semiconductive layer over the insulator layer;
• forming a depletion region within the semiconductive layer, the depletion region being over the peripheral transistor device template portions and over the memory array transistor device template portions, the depletion region being proximate the insulator layer and having a different thickness over the peripheral transistor device template portions than over the memory array transistor device template portions;
• while the depletion region is formed, exposing the semiconductive layer to an electrolytic etching composition to etch the semiconductive layer to about the depletion region, the etched semiconductive layer comprising a different thickness over the peripheral transistor device template portions than over the memory array transistor device template portions;
• forming peripheral transistor devices from the etched semiconductive layer over the peripheral transistor device template portions;
• and
• forming memory array transistor device transistors from the etched semiconductive layer over the memory array transistor device template portions.