Nonvolatile reprogrammable interconnect cell with programmable buried bitline

An array of programmable interconnect cells in a semiconductor body for selectively connecting circuit nodes in an integrated circuit comprising

• a plurality of interconnect cells arranged in rows and columns and each programmable to connect and disconnect circuit modes,
• each cell having a first field effect switch transistor aligned with first field effect transistors of other cells in a first column, a second field effect sense transistor aligned with second field effect transistors of other cells in a second column, and a buried bitline in juxtaposition with the first field effect transistor and the second field effect transistor and aligned with buried bitlines in a third column, each cell being aligned with other cells in the same row,
• each cell having a first polysilicon line running between and spaced from source/drains of the first field effect transistor, between and spaced from source/drains of the second field effect transistor and over the buried bitline and functioning as a common floating gate, a second polysilicon line overlying the first polysilicon line and functioning as a common control gate, the second polysilicon line extending to other cells in a row, and a tunnel oxide separating the first polysilicon line and the buried bitline whereby programming of a cell is effected through the buried bitline, and the sensing of conducting and nonconducting states of a node is through the second field effect transistor.

An array of programmable interconnect cells in a semiconductor body for selectively connecting circuit nodes in an integrated circuit comprising

• a plurality of interconnect cells arranged in rows and columns and each programmable to connect and disconnect circuit nodes, each cell including
• a) a field effect switch transistor formed in the semiconductor body abutting the major surface, said switch transistor having first and second source/drains connected to a first and a second circuit node, a floating gate for storing charge, and a control gate for turning said first field effect transistor on and off responsive to charge on the floating gate,
• b) a field effect sense transistor formed in the semiconductor body abutting the major surface and spaced from the switch transistor, said sense transistor having first and second source/drains, a floating gate for storing charge, and a control gate for turning said sense transistor on and off responsive to charge on the floating gate, and
• c) a buried bitline formed in the semiconductor body abutting the major surface in juxtaposition with the switch transistor and the sense transistor, a floating gate overlying the buried bitline and separated therefrom by a tunnel oxide, and a control gate overlying the floating gate, the floating gate of the switch transistor, the sense transistor and the buried bitline being interconnected, and the control gate of the switch transistor, the sense transistor, and the bitline being interconnected.