US 5,998,879 AGranted

Semiconductor memory device

AssigneeNEC Corporation

InventorsHiroaki Iwaki, Kouichi Kumagai

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Abstract

In a CMOS SRAM cell formed on an SOI substrate and including a flip-flop having first and second NMOS and PMOS transistors, transfer gates having first and seconf MOS transistors, and a word line section, characterized in that:the word line section extends along a predetermined direction; that source and drain diffusion layer regions of the first and second NMOS and PMOS transistors are arranged along the predetermined direction, and gates of these NMOS and PMOS transistors are arranged on channel regions thereof in a direction perpendicular to the predetermined direction; that the gates of the first and second NMOS transistors are electrically connected to the gates of the first and second PMOS transistors, respectively; and that in regions between the gates of the first and second NMOS transistors on the channel regions and the gates of the first and second PMOS transistors on the channel regions, each of the drain diffusion layer regions of the fisrt and second NMOS and PMOS transistors, and each one of the drain and source diffusion layer regions of the first and second MOS transistors are respectively arranged to be adgacent to each other and are electrically connected to each other, respectively, through a diffusion layer interconnection.

Claims30

Dependent claims

A CMOS SRAM cell formed on an SOI substrate and comprising a flip-flop having first and second NMOS transistors and first and second PMOS transistors, transfer gates having first and second MOS transistors, and a word line section,

wherein said word line section extends along a predetermined direction,
wherein source and drain diffusion layer regions of said first and second NMOS transistors and said first and second PMOS transistors are arranged along the predetermined direction, and gates of said first and second NMOS transistors and said first and second PMOS transistors are arranged on channel regions thereof in a direction perpendicular to the predetermined direction,
wherein the gate of said first NMOS transistor is electrically connected to the gate of said first PMOS transistor,
wherein the gate of said second NMOS transistor is electrically connected to the gate of said second PMOS transistor,
wherein in a region between the gate of said first NMOS transistor on a channel region thereof and the gate of said first PMOS transistor on a channel region thereof, the drain diffusion layer region of said first NMOS transistor, the drain diffusion layer region of said first PMOS transistor, and one of the drain and source diffusion layer regions of said first MOS transistor are arranged to be adjacent to each other and are electrically connected to each other through a diffusion layer interconnection,
and wherein in a region between the gate of said second NMOS transistor on a channel region thereof and the gate of said second PMOS transistor on a channel region thereof, the drain diffusion layer region of said second NMOS transistor, the drain diffusion layer region of said second PMOS transistor, and one of the drain and source diffusion layer regions of said second MOS transistor are arranged to be adjacent to each other and are electrically connected to each other through a diffusion layer interconnection.

3 more elements

A semiconductor device, comprising:

a substrate;
first region means of a first conductive type, formed on said substrate, for providing first and second gate transfer transistors and first and second flip-flop transistors, each of said first and second gate transfer transistors each having a source/drain region that corresponds to a source/drain region of a respective one of said first and second flip-flop transistors;
word line means, coupled to at least one gate of said first and second gate transfer transistors, said word line means having a direction on said substrate;
and
second region means of a second conductive type opposite to said first conductive type, said second region means being formed on said substrate adjacent to said first region means, said second region means providing third and fourth flip-flop transistors, each having a source/drain region electrically coupled by a diffusion layer to a source/drain region of a respective one of said first and second flip-flop transistors, a gate of said first flip-flop transistor being coupled to a gate of said third flip-flop transistor and a gate of said second flip-flop transistor being coupled to a gate of said fourth flip-flop transistor, wherein source/drain regions of said flip-flop transistors are oriented in a direction that is substantially parallel to the direction of said word line means.

2 more elements

Dependencies are inferred from the claim text.