Method of manufacturing a laminated wiring structure preventing impurity diffusion therein from N+ and P+ regions in CMOS device with ohmic contact

A method for manufacturing a semiconductor device, the method comprising the steps of:

• (a) providing a semiconductor substrate having a first conductive region having a first conductivity type including a first impurity and a second conductive region having a second conductivity type including a second impurity;
• (b) forming a wiring layer mutually connecting the first and second conductive regions, the wiring layer having a laminated structure and a refractory metal layer having a thickness of about 100 angstroms or less thereunder;
• (c) forming an interlayer insulating layer over the wiring layer;
• and
• (d) rapid thermal annealing the semiconductor substrate after step (c), while preventing the first and second impurities from counter-diffusing from the interconnected first conductive region into the second conductive region through the refractory metal layer.

A method of manufacturing a semiconductor device, the method comprising the steps of:

• (a) providing a semiconductor substrate having first and second conductive regions;
• (b) depositing a titanium layer having a thickness of about 100 angstroms or less over the semiconductor substrate;
• (c) depositing a titanium nitride layer over the titanium layer to provide a laminated conductive wiring layer mutually connecting the first and second conductive regions;
• (d) forming an interlayer insulating layer over the laminated conductive wiring layer;
• and
• (e) rapid thermal annealing the semiconductor substrate to provide an ohmic contact between the refractory metal layer and the semiconductor substrate.

A method for manufacturing a semiconductor device, the method comprising the steps of:

• (a) providing a silicon substrate having a first conductive region of a first conductivity type and a second conductive region having a second conductivity type opposite to the first conductivity type;
• (b) depositing a refractory metal layer having a thickness of about 100 angstroms or less on the silicon substrate;
• (c) forming a counter-diffusion barrier layer over the refractory metal layer;
• (d) patterning said barrier layer and said refractory metal layer, to provide a laminated conductive wiring mutually connecting the first and second conductive regions;
• (e) forming an interlayer insulating layer over the laminated conductive wiring;
• and
• (f) rapid thermal annealing the silicon substrate after step (e) to provide ohmic contact between the refractory metal layer and the silicon substrate.

A method for manufacturing a semiconductor device, the method comprising the steps of:

• (a) providing a silicon substrate having a first conductive region of a first conductivity type including a first impurity and a second conductive region having a second conductivity type opposite to the first conductivity type including a second impurity;
• (b) forming a wiring laminate including a refractory metal layer having a thickness of about 100 angstroms or less on said silicon substrate and contacting said first and second conductive regions, a counter-diffusion barrier layer on said refractory metal layer and an upper conductive layer on said barrier layer;
• (c) patterning said wiring laminate to form an interconnection interconnecting said first and second conductive regions;
• (d) forming an interlayer insulating layer over the wiring layer;
• and
• (e) rapid thermal annealing the silicon substrate after step (d), for a time period sufficiently long to form a first refractory metal silicide at an interface between said refractory metal layer and said first and second conductive regions, and not long enough to convert a full thickness of said refractory metal layer to said first refractory metal silicide.