Method of reducing offset for ion-implantation in semiconductor devices

Abstract

Programming of a plurality of mask ROMs having a common structure and formed on a semiconductor wafer is effected by an ion implantation for adjusting the threshold voltage of the memory transistors. The mask ROMs on the wafer is grouped in a plurality of groups arranged in point-symmetry or axisymmetry. During forming a photoresist pattern for each of the mask ROMs, a common alignment offset is assigned to the photoresist patterns of the mask ROMs in each group in the location of opening for ion implantation. Ion implantation is effected to the mask ROMs by using the photoresist patterns having respective alignment offsets in openings. During the ion implantation, the difference in incident angle of an ion beam between the positions on the wafer is compensated by the alignment offsets in the opening of the photoresist patterns.

Dependencies are inferred from the claim text.