Method for depositing a tungsten layer on silicon
AssigneeMicron Technology, Inc.
InventorsRavi Iyer, Irina Vasilyeva
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AssigneeMicron Technology, Inc.
InventorsRavi Iyer, Irina Vasilyeva
Estimating the term…
This invention is a process for depositing tungsten metal on a silicon surface with the deposited layer having improved uniformity of thickness over prior art deposition techniques. The process involves the steps of removing any native silicon dioxide present on the silicon surface, forming a barrier layer which overlies the silicon surface which prevents the upward diffusion of silicon atoms from the polycrystalline surface, and depositing a final tungsten metal layer on top of the barrier layer. The barrier layer is preferably a refractory metal nitride. It may be formed directly by chemical vapor deposition, by reactive sputtering, or it may be formed indirectly by depositing a preliminary tungsten metal layer, subjecting the preliminary layer to a plasma formed from NH.sub.3 and N.sub.2 gases. Both preliminary and final tungsten metal layers are deposited preferably via chemical vapor deposition using the WF.sub.6 and SiH.sub.4 as reactants.
A process for forming a tungsten metal layer on a polycrystalline silicon surface, said process comprising the steps of:
A process for forming a tungsten metal layer on a polycrystalline silicon surface, said process comprising the steps of:
A process for forming a tungsten metal layer on a polycrystalline silicon layer, said process comprising the steps of:
A process for forming a tungsten metal layer on a polycrystalline silicon layer, said process comprising the steps of:
A process for forming a tungsten metal layer on a polycrystalline silicon layer, said process comprising the steps of:
A process for forming on a silicon substrate partially covered by field isolation regions a conductive sandwich structure from which gate electrodes and interconnect lines can be patterned, said process comprising the steps of:
A process for forming on a silicon substrate partially covered by field isolation regions a conductive sandwich structure from which gate electrodes and interconnect lines can be patterned, said process comprising the steps of:
Dependencies are inferred from the claim text.