US 5,708,621 A · Semiconductor memory with improved word line structure

Abstract

According to one aspect of the invention, a semiconductor memory has, as word lines, a layer of high-resistance signal lines that are paralleled in a separate layer by low-resistance signal lines. Each high-resistance signal line is divided into segments separated by gaps. Interconnections between the high- and low-resistance signal lines in each word line are aligned with the gaps in the high-resistance signal lines in the adjacent word lines. According to a second aspect of the invention, the low-resistance signal lines extend, from alternate directions, to approximately the midpoints of the high-resistance signal lines. The high-resistance signal lines are undivided, or are divided into only two segments apiece. The high- and low-resistance signal lines are interconnected at the midpoints, or at the midpoints and one end.

Claims23

Dependent claims

A semiconductor memory having a plurality of memory cells, comprising:

a plurality of drivers for generating signals that select said memory cells;
a plurality of mutually parallel first signal lines disposed in a first layer, said memory cells being connected to said first signal lines, each of said first signal lines being divided into at least two collinear segments separated by gaps, and said first signal lines having a first electrical resistivity;
a like plurality of second signal lines disposed in a second layer, different from said first layer, said second signal lines running parallel to said first signal lines, said second signal lines being coupled, respectively, to said plurality of drivers, and said second signal lines having a second electrical resistivity less than said first electrical resistivity;
and
a plurality of interconnecting plugs electrically connecting said first signal lines to said second signal lines, said plugs connected to one of said first signal lines being respectively disposed near said gaps in an adjacent one of said first signal lines.

2 more elements

A semiconductor memory having memory cells organized into at least one array, comprising:

a plurality of first drivers disposed on a first side of said array, for generating signals that select said memory cells;
a plurality of second drivers disposed on a second side of said array opposite to said first side, for generating signals that select said memory cells;
a plurality of mutually parallel first signal lines disposed in a first layer, said first signal lines extending across said array from said first side to said second side, said memory cells being connected to said first signal lines, and said first signal lines having a first electrical resistivity;
a plurality of second signal lines disposed in a second layer parallel to said first layer, said second signal lines being coupled to respective first drivers, said second signal lines extending from said first side of said array to a central area disposed midway between said first side and said second side, said second signal lines being coupled to respective first signal lines in said central area, and said second signal lines having a second electrical resistivity less than said first electrical resistivity;
a plurality of third signal lines disposed in said second layer, said third signal lines being coupled to respective second drivers, said third signal lines extending from said second side of said array to said central area, said third signal lines being coupled to respective first signal lines in said central area, and said third signal lines also having said second electrical resistivity;
wherein each one of said first signal lines is electrically coupled to just one corresponding signal line among said second signal lines and said third signal lines;
and
the first signal lines electrically coupled to said second signal lines are disposed alternately with the first signal lines electrically coupled to said third signal lines, as viewed in a direction perpendicular to said first signal lines.

5 more elements

A semiconductor memory having memory cells organized into at least one array, comprising:

a plurality of first drivers disposed on a first side of said array, for generating signals that select said memory cells;
a plurality of second drivers disposed on a second side of said array opposite to said first side, for generating signals that select said memory cells;
a plurality of mutually parallel first signal lines disposed in a first layer, said memory cells being connected to said first signal lines, said first signal lines having a first electrical resistivity, and said first signal lines being divided into respective first segments and second segments, said first segments extending from said first side of said array to a central area disposed midway between said first side and said second side, said second segments extending from said second side of said array to said central area, and said first segments being separated from respective second segments by respective gaps in said central area;
a plurality of second signal lines disposed in a second layer, said second signal lines being coupled to respective first drivers, said second signal lines extending from said first side of said array to said central area, said second signal lines being coupled to the first segments of respective first signal lines at said first side of said array, said second signal lines being coupled to the second segments of respective first signal lines in said central area, and said second signal lines having a second electrical resistivity less than said first electrical resistivity;
a plurality of third signal lines disposed in said second layer, said third signal lines being coupled to respective second drivers, said third signal lines extending from said second side of said array to said central area, said third signal lines being coupled to the second segments of respective first signal lines at said second side of said array, said third signal lines being coupled to the first segments of respective first signal lines in said central area, and said third signal lines also having said second electrical resistivity;
wherein
each one of said first signal lines is electrically coupled to just one corresponding signal line among said second signal lines and said third signal lines;
and
the first signal lines electrically coupled to said second signal lines are disposed alternately with the first signal lines electrically coupled to said third signal lines, as viewed in a direction perpendicular to said first signal lines.

6 more elements

Dependencies are inferred from the claim text.

Semiconductor memory with improved word line structure

Life of this patent

Semiconductor memory with improved word line structure

Life of this patent

Abstract

Claims23