Semiconductor device having damascene interconnects
AssigneeTexas Instruments Incorporated
InventorShin-Puu Jeng
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AssigneeTexas Instruments Incorporated
InventorShin-Puu Jeng
Estimating the term…
This is a device and method of optimizing capacitance and performance for multilevel interconnects. The device comprising: a semiconductor layer 70; a first high-k layer 68 above the semiconductor layer; a first insulating layer 66 above the first high-k layer 68; an interconnect layer 58 above the first insulating layer 66; a second insulating layer 64 around the interconnect layer 58; and a second high-k layer 52 above the second insulating layer 64 and the interconnect layer 58. The device may have a low-k material inserted between closely spaced metal interconnects. Alternatively, the device may have air gaps between closely spaced metal interconnects. In addition, the first high-k layer may be used as an oxide etch stop.
An interconnect structure in a semiconductor device comprising:
An interconnect structure in a semiconductor device comprising:
An interconnect structure in a semiconductor device comprising:
An interconnect structure in a semiconductor device comprising:
Dependencies are inferred from the claim text.