Silicide agglomeration fuse device
AssigneeIntel Corporation
InventorsMark T. Bohr, Mohsen Alavi
Life of this patent
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Abstract
A fusible link device disposed on a semiconductor substrate for providing discretionary electrical connections. The fusible link device of the invention includes a silicide layer and a polysilicon layer formed on the silicide layer and has a first un-programmed resistance. The silicide layer agglomerates to form an electrical discontinuity in response to a predetermined programming potential being applied across the silicide layer, such that the resistance of the fusible link device can be selectively increased to a second programmed resistance.
Claims22
A fusible link device disposed on a semiconductor substrate for providing discretionary electrical connections, the fusible link device comprising:
- a polysilicon layer having a first resistance;
- a silicide layer formed on the polysilicon layer, the silicide layer having a second resistance lower than the first resistance, the silicide layer agglomerating to form an electrical discontinuity in response to a predetermined programming potential being applied across the silicide layer, such that the resistance of the fusible link device can be selectively increased;
- and
- nine contacts electrically coupled to either end of the silicide layer for receiving the programming potential.
A fuse disposed on a semiconductor substrate, and having a first un-programmed resistance, the fuse comprising:
- a polysilicon layer;
- a silicide layer formed on the polysilicon layer, the silicide layer agglomerating to form an electrical discontinuity in response to a predetermined programming potential being applied across the silicide, layer, such that the resistance of the fuse can be selectively increased to a second programmed resistance;
- and
- nine contacts electrically coupled to either end of the silicide layer for receiving the programming potential.
A fusible link device disposed on a semiconductor substrate for providing discretionary electrical connections, the fusible link device comprising:
- a polysilicon layer having a first resistance, the polysilicon layer including a first region doped n-type and at least a second region doped p-type to form at least one p-n junction in the polysilicon layer;
- and
- a silicide layer formed on the polysilicon layer, the silicide layer having a second resistance lower than the first resistance, the silicide layer agglomerating to form an electrical discontinuity in response to a predetermined programming potential being applied across the silicide layer, such that the resistance of the fusible link device can be selectively increased.
A fuse disposed on a semiconductor substrate, and having a first un-programmed resistance, the fuse comprising:
- a polysilicon layer, the polysilicon layer including a first region doped n-type and at least a second region doped p-type to form at least one p-n junction in the polysilicon layer;
- and
- a silicide layer formed on the polysilicon layer, the silicide layer agglomerating to form an electrical discontinuity in response to a predetermined programming potential being applied across the silicide layer, such that the resistance of the fuse can be selectively increased to a second programmed resistance.
A method for forming a fuse comprising the steps of:
- forming a polysilicon layer on a semiconductor substrate;
- doping the polysilicon layer n-type;
- forming p-type regions in the n-type polysilicon layer such that the polysilicon layer includes at least one p-n junction;
- forming a silicide layer on the polysilicon layer;
- and
- forming contacts at either end of the silicide layer, the contacts being electrically coupled to the silicide layer such that a programming potential may be applied across them to program the fuse device.
Dependencies are inferred from the claim text.