Pad protection diode structure

An integrated circuit comprising:

• a first power pad;
• a second power pad;
• a third pad to receive a signal;
• and
• a protection structure that protects the third pad, the protection structure including a plurality of regions including a plurality of P regions and a plurality of N regions that together form a plurality of PN junctions, each of the plurality of PN junctions being formed at a physical intersection between one of the plurality of P regions and one of the plurality of N regions, at least one of the plurality of regions being a lowly doped region, the protection structure being arranged so that every path between the first power pad and the second power pad passes through the lowly doped region and at least three of the plurality of PN junctions, wherein at least one of the plurality of regions forms a portion of a diode disposed between the second power pad and the third pad to protect the third pad, wherein another one of the plurality of regions forms a substrate such that the diode is disposed outside the substrate, and wherein the plurality of regions is arranged to prevent carrier flow from the diode from causing a latch-up condition between the first power pad and the second power pad.

An integrated circuit, comprising:

• a first pad to receive a signal;
• a second power pad to a receive a supply reference;
• a component;
• and
• a protection structure, coupled between the first pad and the second power pad, that protects the first pad, the protection structure including a first portion adjacent the component and a second portion, wherein the first portion has a first conduction junction with a first voltage threshold, wherein the second portion has a second conduction junction with a second voltage threshold, and wherein the first and the second voltage thresholds are different.

A protection structure for protecting a first pad of an integrated circuit, the integrated circuit having a second pad to receive a supply voltage, the protection structure comprising:

• a first region of a first conductivity type coupled to the first pad;
• a second region of a second conductivity type having a first highly doped area coupled to the second pad and a lowly doped area;
• and
• a substrate of the second conductivity type contacting the first and second regions, wherein the lowly doped area of the second region is disposed between the first highly doped area of the second region and the substrate, and wherein a diode is formed outside the substrate between the first and second regions.