US 5,707,899 A · SOI structure with a deep thin oxide layer prepared by ION implantation at high energy followed by thermal treatment

Abstract

A process for preparing an SOI structure with a deep thin oxide layer which comprises, in succession, a first ion implantation at an oxygen fluence within the range of 10.sup.15 -10.sup.16 ions/cm.sup.2, thermal treatment at a temperature within the range of 600.degree.-900.degree. C., a second ion implantation at an oxygen fluence within the range of 2.times.10.sup.17 -8.times.10.sup.17 ions/cm.sup.2, and a final thermal treatment at a temperature within the range of 1150.degree.-1400.degree. C.

Claims1

Dependent claims

A process for preparing an SOI structure with a deep thin oxide layer, having a thickness between 80 nm and 150 nm, comprising the following stages in succession:

a first ion implantation at an oxygen fluence within the range of 10.sup.15 -10.sup.16 ions/cm.sup.2 ;
thermal treatment at a temperature within the range of 600.degree.-900.degree. C.;
a second ion implantation at an oxygen fluence within the range of 2.times.10.sup.17 -8.times.10.sup.17 ions/cm.sup.2 ;
final thermal treatment at a temperature within the range of 1150.degree.-1400.degree. C.

1 more element

Dependencies are inferred from the claim text.

Facts

Application

08/302,091Filed 7 Sep 1994 · continuation

Priority

IT MI92A117115 May 1992

Granted

13 Jan 1998

Term ends

Not estimatedThe source records don’t support an estimate.

Classification5 codes

H10P 30/209
Of electrically inactive species: in silicon to make buried insulating layers
H10P 90/1908
Preparing SOI wafers: using silicon implanted buried insulating layers, e.g. oxide layers [SIMOX]
H10W 10/181
Isolation regions comprising dielectric materials: semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers
H10P
Generic processes or apparatus for the manufacture or treatment of devices covered

Abstract

Facts

Application

08/302,091Filed 7 Sep 1994 · continuation

Priority

IT MI92A117115 May 1992

Granted

13 Jan 1998

Term ends

Not estimatedThe source records don’t support an estimate.

Classification5 codes

H10P 30/209
Of electrically inactive species: in silicon to make buried insulating layers
H10P 90/1908
Preparing SOI wafers: using silicon implanted buried insulating layers, e.g. oxide layers [SIMOX]
H10W 10/181
Isolation regions comprising dielectric materials: semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers
H10P
Generic processes or apparatus for the manufacture or treatment of devices covered

SOI structure with a deep thin oxide layer prepared by ION implantation at high energy followed by thermal treatment

Life of this patent

Abstract

Claims1

SOI structure with a deep thin oxide layer prepared by ION implantation at high energy followed by thermal treatment

Life of this patent

Abstract

Claims1