Method for preventing delamination of interlevel dielectric layer over FET P.sup.+ doped polysilicon gate electrodes on semiconductor integrated circuits

A method for fabricating P-channel and N-channel field effect transistors (FETs) with improved P-channel FETs for CMOS circuits comprising the steps of:

• providing a semiconductor substrate having device areas surrounded and electrically isolated by field oxide regions, said device areas having N-wells for P-channel FETs and P-wells for N-channel FETs;
• forming a gate oxide on said N- and P-wells;
• depositing a polysilicon layer on said substrate and doping said polysilicon over said P-wells with an N-type dopant and doping said polysilicon over said N-wells with a P-type dopant;
• patterning said polysilicon layer and thereby forming gate electrodes for said N-channel and said P-channel FETs;
• masking said N-wells with a photoresist mask and implanting lightly doped N- source/drain regions in said P-wells adjacent to said gate electrodes;
• masking said P-wells with a photoresist mask and implanting lightly doped P- source/drain regions in said N-wells adjacent to said gate electrodes;
• depositing a conformal first insulating layer over said gate electrodes and elsewhere over said substrate;
• anisotropically etching back said first insulating layer and thereby forming sidewall spacers on said gate electrodes;
• masking said N-wells with a photoresist mask and implanting N.sup.+ source/drain regions in said P-wells adjacent to said sidewall spacers;
• masking said P-wells with a photoresist mask and implanting P.sup.+ source/drain regions in said N-wells adjacent to said sidewall spacers using BF.sub.2 ions;
• annealing said substrate and degassing fluorine atoms from said P-channel gate electrodes;
• depositing a conformal second insulating layer composed of silicon nitride (Si.sub.3 N.sub.4) over said gate electrodes and elsewhere on said substrate;
• depositing a third insulating layer composed of borophosphosilicate glass (BPSG) on said second insulating layer and leveling by thermal anneal said third insulating layer, said prior degassing anneal of said fluorine atoms from said P-channel FET gate electrodes preventing void formation between said P-channel gate electrodes and said second insulating layer during said thermal anneal and subsequent high-temperature processing.