Process for fabricating a contactless electrical erasable EPROM memory device

A product made by the process of fabricating a matrix of memory cells having a floating gate organized in rows and columns, with bitlines in the form of diffused regions alternately continuous and contacted directly through a metal line and discontinuous and contacted through respective select transistors arranged along at least two rows of offset cells every certain number of rows of matrix's memory cells, on a semiconducting substrate having a first type of conductivity and comprising the steps of:

• forming an pad oxide layer on said substrate, depositing and defining a masking nitride layer;
• forming a field oxide defining channel regions of said cells in the form of parallel strips oriented along a first direction and rows of offset insular areas of said select transistors and of said contacts of said continuous bitlines;
• removing said masking nitride and said pad oxide;
• thermally growing a layer of gate oxide over said channel regions and said insular areas defined by the field oxide;
• defining by masking the area of said matrix of memory cells, etching said gate oxide and implanting a dopant of said first type of conductivity in said channel areas of the memory cells and removing said mask and growing a layer of tunnel oxide having a thickness smaller than the thickness of said removed gate oxide layer;
• depositing a layer of polycrystalline silicon of first level and doping the polycrystalline silicon for increasing electrical conductivity to a desired value, forming a interpoly insulating multilayer;
• masking said interpoly insulating multilayer;
• etching said interpoly isolation multilayer, said doped polycrystalline silicon layer of first level, said gate or tunnel oxide and said field oxide at crossings until exposing said semiconducting substrate along a plurality of alternately continuous and interrupted strips parallel to each other and oriented orthogonally in respect to underlying strips of field oxide defining said strip-shaped channel regions, within the area occupied by said matrix of cells and leaving strips of said interpoly multilayer and doped polycrystalline silicon of first level in the matrix's area;
• masking areas external to the matrix's area and implanting a heavy dose of a dopant capable of producing a second type of conductivity in exposed areas of said semiconducting substrate within said matrix area to form matrix's bitlines, each coinciding either with source or with drain regions of a second type of conductivity of memory cells arranged along a same column;
• diffusing said implanted dopant and oxidizing the surface of said semiconducting substrate in said areas exposed and implanted during the preceding steps and forming again a gate oxide layer in the areas of said select transistors and of external circuits;
• masking the matrix's area and etching said interpoly insulating multilayer, said doped polycrystalline silicon of first level and said gate oxide and removing said mask;
• masking the area occupied by said memory cells and implanting a dopant of said first type of conductivity for adjusting the threshold in the channel areas of said select transistors and of transistors of circuits external to the matrix of memory cells, through said reformed gate oxide layer;
• depositing and doping a layer of polycrystalline silicon of second level;
• depositing a layer of tungsten silicide;
• masking said tungsten silicide layer to define the gate of transistors of said external circuits as well as of said select transistors and the control gates of said matrix of memory cells in the form of parallel strips oriented in said first direction;
• etching said tungsten silicide layer and said doped polycrystalline silicon layer of second level arresting the etching on said field oxide in areas external to the area of said matrix of memory cells and on said interpoly isolation multilayer within the matrix's area;
• masking the areas external to said matrix area;
• performing a self aligned etching of said interpoly isolation multilayer and of said doped polysilicon layer of first level within said matrix's area;
• planarizing the surface by depositing a layer of planarizing dielectric material followed by etching and depositing an intermediate isolation dielectric layer;
• forming a plurality of contacts on each of said continuous bitlines disposed alternately to said interrupted bitlines and depositing and defining parallel lines of a metallization layer over each of said plurality of contacts of said continuous bitlines.

A product made by the process of for fabricating an electrically erasable nonvolatile memory having a matrix of floating gate memory cells organized in rows and columns, in which first bitlines, which are continuous and are contacted directly by a metal line, are alternated with second bitlines, which are discontinuous and are contacted through respective select transistors, comprising the steps of:

• (a.) forming, in a substrate having surface semiconducting regions of a first conductivity type, a field oxide defining channel regions of said cells in the form of parallel strips oriented along a first direction, and rows of offset insular areas of said select transistors and of said contacts to said first bitlines;
• (b.) forming, over said channel regions and said insular areas defined by said field oxide, a layer of gate oxide outside said matrix, and a tunnel oxide, which is thinner than said gate oxide, inside said matrix;
• (c.) forming a first polysilicon layer, an interpoly dielectric thereover, a protective polysilicon layer thereover, and a layer of silicon nitride thereover;
• (d.) patterning, in a stack etching step, said silicon nitride layer, said protective polysilicon layer, said interpoly dielectric, said first polysilicon layer, and said gate and tunnel and field oxides where exposed thereunder, to expose said semiconducting substrate along a plurality of alternately continuous and interrupted strips parallel to each other and oriented orthogonally to said first direction within said matrix;
• (e.) implanting a heavy dose of a second-conductivity-type dopant, to form diffused bitlines in exposed areas of said semiconducting substrate;
• (f.) oxidizing said exposed areas of said semiconducting substrate while diffusing said implanted dopant, said silicon nitride layer meanwhile providing an oxidation barrier where present;
• (g.) depositing a conformal dielectric material, and performing a planarizing etchback to remove said silicon nitride layer and expose said protective layer of polycrystalline silicon;
• (h.) removing said protective polysilicon layer and said interpoly dielectric from areas outside of said matrix;
• (i.) forming a second polysilicon layer, and etching said second polysilicon layer to define the gates of transistors of said external circuits as well as of said select transistors and the control gates of said matrix of memory cells in the form of parallel strips oriented in said first direction, and performing an additional etching step, within said matrix, to remove said interpoly dielectric and said first polysilicon layer where not covered by said second polysilicon layer;
• and
• (j.) forming a plurality of contacts on each of said first bitlines, and depositing and defining parallel lines of a metallization layer to make contact thereto.

A product made by the process of fabricating an electrically erasable nonvolatile memory having a matrix of floating gate memory cells organized in rows and columns, in which first bitlines, which are continuous and are contacted directly by a metal line, are alternated with second bitlines, which are discontinuous and are contacted through respective select transistors, comprising the steps of:

• (a.) forming, in a substrate having surface semiconducting regions of a first conductivity type, a field oxide defining channel regions of said cells in the form of parallel strips oriented along a first direction, and rows of offset insular areas of said select transistors and of said contacts to said first bitlines;
• (b.) forming, over said channel regions and said insular areas defined by the field oxide, a layer of gate oxide outside said matrix, and a tunnel oxide, which is thinner than said gate oxide, inside said matrix;
• (c.) forming a first polysilicon layer, and an interpoly dielectric thereover;
• (d.) patterning, in a stack etching step, said interpoly dielectric, said first polysilicon layer, and said gate and tunnel and field oxides where exposed thereunder, to expose said semiconducting substrate along a plurality of alternately continuous and interrupted strips parallel to each other and oriented orthogonally to said first direction within said matrix, while leaving strips of said interpoly dielectric and first polysilicon layer within said matrix;
• (e.) implanting a heavy dose of a second-conductivity-type dopant into exposed areas of said semiconducting substrate within said matrix, to form diffused bitlines;
• (f.) oxidizing said exposed areas of said semiconducting substrate while diffusing said implanted dopant;
• (g.) removing said interpoly dielectric and first polysilicon layer from areas outside said matrix;
• (h.) forming a second polysilicon layer, and etching said second polysilicon layer to define the gates of transistors of said external circuits as well as of said select transistors and the control gates of said matrix of memory cells in the form of parallel strips oriented in said first direction, and performing an additional etching step, within said matrix, to remove said interpoly dielectric and said first polysilicon layer where not covered by said second polysilicon layer;
• (i.) performing planarization by depositing and etching back a layer of conformal dielectric material, and depositing an intermediate isolation dielectric layer;
• and
• (j.) forming a plurality of contacts on each of said first bitlines and depositing and defining parallel lines of a metallization layer over each of said plurality of contacts of said continuous bitlines.