Method of fabricating high density integrated circuits, containing stacked capacitor DRAM devices, using elevated trench isolation and isolation spacers

A method for fabricating a stacked capacitor structure, dynamic random access memory, (DRAM), device, on a semiconductor substrate, with increased capacitor surface area available via use of elevated shallow trench isolation and insulator sidewall spacers, comprising the steps of:

• growing a gate dielectric layer on the surface of said semiconductor substrate;
• depositing a first polysilicon layer on said gate dielectric layer;
• depositing a first insulator layer on said first polysilicon layer;
• patterning of said first insulator layer, of said first polysilicon layer, and of said semiconductor substrate, to a create a shallow trench;
• depositing a second insulator layer on the top surface of said first insulator layer, and completely filling said shallow trench;
• removal of said second insulator layer, and of said first insulator layer, from the top surface of said first polysilicon layer, resulting in said elevated shallow trench, filled with said second insulator layer, raised above top surface of said semiconductor substrate by an amount equal to the thickness of said first polysilicon layer;
• deposition of a first tungsten silicide layer on the top surface of said first polysilicon layer, and on top surface of said second insulator layer, in said elevated shallow trench;
• deposition of a third insulator layer on said first tungsten silicide layer;
• patterning of said third insulator layer, of said first tungsten silicide layer, and of said first polysilicon layer, to create a polycide gate structure, on said gate dielectric layer, while patterning of said third insulator layer, and of said first tungsten silicide layer, to create a metal land structure on top surface of said second insulator layer, in said elevated shallow trench, with top surfaces of both said polycide gate structure and said metal land structure, at the same topographical level;
• deposition of a fourth insulator layer;
• anisotropic etching of said fourth insulator layer to create a first insulator spacer, on the sidewalls of said polycide gate structure, and on the sidewalls of said metal land structure, while removing said gate dielectric layer from regions not covered by said polycide gate structures;
• ion implanting a first conductivity imparting dopant into said semiconductor substrate, in regions not covered by said polycide gate structures, to form source and drain regions;
• depositing a second polysilicon layer on the top surface of said third insulator layer of said polycide gate structures, and of said metal land structures, and completely filling spaces between said polycide gate structures, and between said polycide gate structures and said metal land structures;
• depositing a second tungsten silicide layer on said second polysilicon layer;
• depositing a fifth insulator layer on said second tungsten silicide layer;
• patterning of said fifth insulator layer, of said second tungsten silicide layer, and of said second polysilicon layer, to create a bit line contact structure, to said source and drain region, between said polycide gate structures, partially overlying said polycide gate structures, while leaving some said second polysilicon layer in spaces between said polycide gate structures and said metal land structures;
• depositing a sixth insulator layer;
• anisotropic etching of said sixth insulator layer to create a second insulator spacer on the sidewalls of said bit line contact structure;
• deposition of a third polysilicon layer on the top surface of said bit line contact structures, on the top surface of said polycide gate structures, not covered by said bit line contact structures, on the top surface of said metal land structures, not covered by said bit line contact structures, and on said second polysilicon layer remaining in spaces between said polycide gate structures and said metal land structures;
• patterning of said third polysilicon layer to create a storage node structure, of said stacked capacitor structure, between said bit line contact structures, with increased surface area resulting from said storage node structure exhibiting raised features in regions where said storage node structure overlies said bit line contact structure, and elevated shallow trench;
• forming a capacitor dielectric layer on said storage node structure;
• depositing a fourth polysilicon layer on said capacitor dielectric layer, on said storage node structure, and on top surface of said bit line contact structures, not covered by said storage node structures;
• and
• patterning of said fourth polysilicon layer to form cell plate structure of stacked capacitor structure.

A stacked capacitor structure, dynamic random access memory, (DRAM), device, on a semiconductor substrate, comprising:

• insulator filled, elevated shallow trench isolation regions;
• polycide gate structures, on said semiconductor substrate, between said insulator filled, elevated shallow trench regions;
• metal land structures, on said insulator filled, shallow trench regions;
• first insulator spacers on sidewalls of said polycide gate structures;
• source and drain regions in areas of said semiconductor substrate, not covered by said polycide gate structures;
• bit line contact structures between said polycide gate structures, contacting said source and drain regions, and partially overlying said polycide gate structures;
• said bit line contact structures contacting said source and drain regions, and partially overlying said metal land structures on said insulator filled, shallow trench;
• second insulator spacers on sidewalls of said bit line contact structures;
• and
• said stacked capacitor structure, between said bit line contact structures, contacting said source and drain region, and partially overlying said bit line contact structures, with lower electrode of said stacked capacitor structure exhibiting raised features in regions where said lower electrode overlies said bit line contact structure, while exhibiting non-raised features in regions where said lower electrode overlies said source and drain region.