US 5,705,438 AGranted

Method for manufacturing stacked dynamic random access memories using reduced photoresist masking steps

AssigneeVanguard International Semiconductor Corporation

InventorHorng-Huei Tseng

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Abstract

A method for manufacturing stacked dynamic random access memory using reduced photomask steps was achieved. The invention utilizes two masking steps for forming the array of stacked capacitors and bit line contacts. One of the masking steps is used to concurrently form the bit line contact openings and to define the capacitor top electrode area for the stacked capacitors. After forming the array of field effect transistors by conventional means, an array of capacitor bottom electrodes is patterned from an N.sup.+ doped polysilicon layer using the first photoresist mask and plasma etching. An interelectrode dielectric layer is formed on the bottom electrodes. An N.sup.+ doped second poly-silicon layer and insulating layer are deposited. The insulating layer and second polysilicon layer are patterned with a second photoresist mask and plasma etched to concurrently form the bit line contact openings and to define the capacitor top electrode plate. The sidewalls of the exposed second polysilicon layer in the bit line contact openings are then oxidized to prevent the top electrode plate from shorting to the bit lines which are then patterned from a polycide layer that extends over and in the bit line contact openings.

Claims21

Dependent claims

A method for manufacturing stacked capacitors and bit lines for an array of dynamic random access memory (DRAM) cells on a semiconductor substrate comprising the steps of:

providing a semiconductor substrate having device areas surrounded and electrically isolated from each other by field oxide areas;
providing field effect transistors (FETs) in said device areas, each of said transistors having a gate electrode formed from a patterned first polysilicon layer, and having first and second source/drain contact areas in said device areas, and electrically insulated by depositing a conformal first insulating layer thereon;
photoresist masking and anisotropically etching contact openings to said first source/drain contact areas of each said FET, thereby forming node contact openings for said stacked capacitors;
depositing a conformal second poly-silicon layer on said substrate;
patterning said second polysilicon layer using a first photoresist mask and anisotropic plasma etching leaving portions of said second polysilicon layer over and in said first source/drain contact areas thereby forming bottom electrodes for said stacked capacitors;
forming a conformal second insulating layer on said patterned second polysilicon layer thereby forming an interelectrode dielectric layer on said bottom electrodes;
depositing a conformal third polysilicon layer over said second insulating layer and elsewhere on said first insulating layer;
depositing a third insulating layer on said third polysilicon layer;
etching bit line contact openings using a second photoresist mask and anisotropic plasma etching over said second source/drain contact areas of each said FET through said third insulating layer and said third polysilicon layer to the surface of said first insulating layer;
forming a thermal oxide on sidewalls of said third polysilicon layer exposed in said bit line contact openings;
blanket etching and removing said first insulating layer in said bit line contact openings to said second source/drain contact areas of each said FET;
depositing a conformal conducting layer on and in said second source/drain contact areas and elsewhere on said third insulating layer;
patterning by photoresist masking and anisotropic plasma etching said conducting layer to form bit lines extending over said bit line contact openings thereby completing said array of DRAM cells having said stacked capacitors and bit lines.

10 more elements

A method for manufacturing DRAM devices having arrays of stacked capacitors and bit lines on a semiconductor substrate comprising the steps of:

providing a semiconductor substrate having device areas surrounded and electrically isolated from each other by field oxide areas;
providing field effect transistors (FETs) in said device areas, each of said transistors having a gate electrode formed from a patterned first polysilicon layer, and having first and second source/drain contact areas in said device areas, and electrically insulated by depositing a conformal first insulating layer thereon;
photoresist masking and anisotropically etching contact openings to said first source/drain contact areas of each said FET, thereby forming node contact openings for said stacked capacitors;
depositing a conformal second poly-silicon layer on said substrate;
patterning said second polysilicon layer using a first photoresist mask and anisotropic plasma etching leaving portions of said second poly-silicon layer over and in said first source/drain contact areas thereby forming bottom electrodes for said stacked capacitors;
forming a conformal second insulating layer on said patterned second polysilicon layer thereby forming an interelectrode dielectric layer on said bottom electrodes;
depositing a conformal third poly-silicon layer over said second insulating layer and elsewhere on said first insulating layer;
depositing a third insulating layer on said third polysilicon layer;
etching bit line contact openings using a second photoresist mask and anisotropic plasma etching over said second source/drain contact areas of each said FET through said third insulating layer and said third polysilicon layer to the surface said first insulating layer;
forming a thermal oxide on sidewalls of said third polysilicon layer exposed in said bit line contact openings;
blanket etching and removing said first insulating layer in said bit line contact openings to said second source/drain contact areas of each said FET;
depositing a conformal fourth polysilicon/silicide layer on and in said second source/drain contact areas and elsewhere on said third insulating layer;
patterning by photoresist masking and anisotropic plasma etching said poly-silicon/silicide layer to form bit lines extending over said bit line contact openings, and providing further processing to complete the wiring to the peripheral circuits on the DRAM chip thereby completing said DRAM device having said stacked capacitors and bit lines.

10 more elements

Dependencies are inferred from the claim text.