US 5,705,437 AGranted

Trench free process for SRAM

AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.

InventorsYi-Huang Wu, Der-Chen Chen

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Abstract

A method of forming an FET device starts by forming a sacrificial layer over a semiconductor substrate and an outer buried contact region is produced by ion implantation into the substrate, followed by stripping the sacrificial layer, forming a gate oxide layer, and depositing polysilicon over the gate oxide layer. Then, etch an inner buried contact opening through the polysilicon and the gate oxide layer down to the substrate over the outer buried contact region forming an etched buried contact opening. Implant dopant into the substrate through the inner buried contact opening in the second mask to dope the substrate forming the inner buried contact region within the outer buried contact region self-aligned with the etched buried contact opening. Form a blanket, second polysilicon layer over the gate oxide layer reaching down through the etched buried contact opening into electrical and mechanical contact with the inner buried contact region. Etch to form the interconnect and the gate electrode from the polysilicon layers, and form source/drain regions.

Claims22

Dependent claims

A method of formation of a MOSFET device including a gate electrode, source and drain regions, a buried contact and an interconnect connected to said buried contact, comprising the sequence of steps as follows:

providing a silicon semiconductor substrate,
forming a sacrificial silicon dioxide layer over said substrate,
implanting dopant into said substrate forming an outer buried contact region in said substrate,
removing said sacrificial silicon dioxide layer from said substrate,
forming a gate oxide layer over said substrate,
forming a first polysilicon layer over said gate oxide layer,
etching an inner buried contact opening through said first polysilicon layer and said gate oxide layer down to the surface of said substrate over said outer buried contact region to form an etched buried contact opening,
implanting dopant into said substrate through said inner buried contact opening in said second mask to dope said substrate therethrough thereby forming said inner buried contact region within said outer buried contact region self-aligned with said etched buried contact opening,
forming a blanket, second polysilicon layer over said gate oxide layer reaching down through said etched buried contact opening into electrical and mechanical contact with said inner buried contact region,
etching to form said interconnect and said gate electrode from said first and second polysilicon layers, and
implanting dopant into said substrate forming source/drain regions self-aligned with said gate electrode.

8 more elements

providing a silicon semiconductor substrate,
forming a sacrificial silicon dioxide layer over said substrate,
forming a first mask over said sacrificial silicon dioxide layer, said first mask having an opening therethrough for defining an outer buried contact region in said substrate,
implanting dopant into said substrate through said outer buried contact opening is said first mask to dope said substrate therethrough thereby forming said outer buried contact region,
removing said sacrificial silicon dioxide layer from said substrate,
forming a silicon dioxide, gate oxide layer over said substrate,
forming a first polysilicon layer over said gate oxide layer,
forming a second mask over said gate oxide layer said second mask having an inner buried contact opening therethrough for defining an inner buried contact region centered over said outer buried contact region in said substrate,
etching through said inner buried contact opening removing said gate oxide layer and said first polysilicon layer below said inner buried contact opening down to the surface of said substrate over said outer buried contact region to form an etched buried contact opening,
implanting dopant into said substrate through said inner buried contact opening in said second mask to dope said substrate therethrough thereby forming said inner buried contact region within said outer buried contact region self-aligned with said etched buried contact opening,
after stripping of said second mask, forming a blanket, second polysilicon layer over said gate oxide layer reaching down through said etched buried contact opening into electrical and mechanical contact with said inner buried contact region,
forming a third mask over said second polysilicon layer for patterning said second polysilicon layer,
etching through said third mask to define said interconnect and to define said gate electrode from said first and second polysilicon layers,
stripping said third mask from said device, and
implanting dopant into said substrate forming source/drain regions self-aligned with said gate electrode.

12 more elements

Dependencies are inferred from the claim text.