Method of forming semiconductor device having planarized wiring with good thermal resistance
AssigneeYamaha Corporation
InventorSatoshi Hibino
Life of this patent
Estimating the term…
Loading patent…
AssigneeYamaha Corporation
InventorSatoshi Hibino
Estimating the term…
A method of forming conductive wiring on a semiconductor substrate. A plurality of contact holes having different sizes are formed in an insulating film formed on the substrate. A first barrier metal layer is formed on the insulating film, and a tungsten layer is uniformly formed on the first barrier metal layer. The tungsten layer is etched back to form plug-shaped tungsten regions in small contact holes and tapered tungsten regions in large contact holes. The central area of the first barrier metal layer in the large contact hole is exposed. A second barrier metal layer is formed covering the plug-shaped tungsten region and the tapered tungsten region and the exposed first barrier metal layer and sandwiching the plug-shaped and tapered tungsten regions between the first and second barrier metal layers, preventing punch-through of Al atoms from an Al layer to be thereafter formed, into the substrate, even when the first barrier metal layer is damaged during etch-back.
A method for manufacturing a semiconductor device comprising the steps of:
A method for manufacturing a semiconductor device comprising the steps of:
A method for manufacturing a semiconductor device on a substrate comprising the steps of:
A method for manufacturing a semiconductor device, comprising the steps of:
Dependencies are inferred from the claim text.