US 5,705,028 A · Method of manufacturing a semiconductor device with flattened multi-layer wirings

Abstract

A wiring layer formed on a field insulating film covering the surface of a semiconductor substrate is covered with an interlayer film. The interlayer film is covered with a flat film such as spin-on-glass formed by spin coating. The flat film has, for example, a laminated structure of an organic SOG film and an inorganic SOG film. The inorganic SOG film is suitable for obtaining a polishing speed generally equal to that of a CVD oxide film. The insulating film and the flat film are chemical-mechanical polished at a same polishing speed until the flat film is thoroughly removed, to leave a planarized insulating film.

Claims31

Dependent claims

A method of manufacturing a semiconductor device with multi-layer wiring, the method comprising the steps of:

(a) providing a semiconductor substrate having a first level wiring structure thereon;
(b) forming a second level wiring structure on the first level wiring structure;
(c) forming an interlevel insulating film on the second level wiring structure, the interlevel insulating film having a corrugated surface, the interlevel insulating film directly contacting said second level wiring structure;
(d) forming a sacrificial film over the interlevel insulating film, said sacrificial film having non-conformal topography to the underlying interlevel insulating film to form a planar upper surface on the semiconductor device, wherein said forming the sacrificial film over the interlevel insulating film includes:
(d-1) forming a first sacrificial sublayer over the interlevel insulating film directly contacting said second level wiring structure, the first sacrificial sublayer including silanol-based organic spin-on-glass;
and
(d-2) forming a second sacrificial sublayer over the first sacrificial sublayer to provide a laminated structure of the first and second sacrificial sublayers, the second sacrificial sublayer including inorganic spin-on-glass;
and
(e) chemical-mechanical polishing the interlevel insulating film directly contacting said second level wiring structure and the sacrificial film to provide a planarized interlevel insulating film directly contacting said second level wiring structure.

6 more elements

A method of manufacturing a semiconductor device with multi-layer wiring, the method comprising the steps of:

(a) providing an underlying structure of a semiconductor substrate having a first level wiring structure thereon;
(b) forming a first interlevel insulating film over the underlying structure having conformal topography to the underlying structure, said first interlevel insulating film directly contacting said underlying first level wiring structure;
(c) forming a first sacrificial film over the first insulating film, said first sacrificial film having non-conformal topography to the first insulating film and having a substantially planar upper surface, wherein said forming the first sacrificial film over the first insulating film includes:
(c-1) forming a first sacrificial sublayer over the first interlevel insulating film directly contacting said underlying first wiring structure, the first sacrificial sublayer including silanol-based organic spin-on-glass;
and
(c-2) forming a second sacrificial sublayer over the first sacrificial sublayer to provide a laminated structure of the first and second sublayers, the second sacrificial sublayer including inorganic spin-on-glass;
(d) chemical-mechanical polishing the first interlevel insulating film directly contacting said underlying first level wiring structure and the first sacrificial film to provide a planarized first interlevel insulating film directly contacting said underlying first level wiring structure;
(e) forming a second level wiring structure on the planarized first interlevel insulating film;
(f) forming a second interlevel insulating film over the second level wiring structure having conformal topography to the second level wiring structure, said second interlevel insulating film directly contacting said underlying second level wiring structure;
(g) forming a second sacrificial film over the second interlevel insulating film, said second sacrificial film having non-conformal topography to the second interlevel insulating film and having a substantially planar upper surface;
and
(h) chemical-mechanical polishing the second interlevel insulating film directly contacting said underlying second level wiring structure and the second sacrificial film to provide a planarized second interlevel insulating film directly contacting said underlying second level wiring structure.

9 more elements

A method of manufacturing a semiconductor device with multi-layer wiring, the method comprising the steps of:

(a) providing an underlying structure of a semiconductor substrate having a first level wiring structure thereon;
(b) forming a first interlevel insulating film over the underlying structure having conformal topography to the underlying structure, said first interlevel insulating film directly contacting said underlying first level wiring structure;
(c) forming a first sacrificial film over the first insulating film, said first sacrificial film having non-conformal topography to the first insulating film and having a substantially planar upper surface;
(d) chemical-mechanical polishing the first interlevel insulating film directly contacting said underlying first level wiring structure and the first sacrificial film to provide a planarized first interlevel insulating film directly contacting said underlying first level wiring structure:
(e) forming a second level wiring structure on the planarized first interlevel insulating film;
(f) forming a second interlevel insulating film over the second level wiring structure having conformal topography to the second level wiring structure, said second interlevel insulating film directly contacting said underlying second level wiring structure;
(g) forming a second sacrificial film Over the second interlevel insulating film, said second sacrificial film having non-conformal topography to the second interlevel insulating film and having a substantially planar upper surface, wherein said forming the second sacrificial film over the second interlevel insulating film includes:
(g-1) forming a first sacrificial sublayer over the second interlevel insulating film directly contacting said underlying second level wiring structure, the first sacrificial sublayer including silanol-based organic spin-on-glass;
and
(g-2) forming a second sacrificial sublayer over the first sacrificial sublayer to provide a laminated structure of the first and second sublayers, the second sacrificial sublayer including inorganic spin-on-glass;
and
(h) chemical-mechanical polishing the second interlevel insulating film directly contacting said underlying second level wiring structure and the second sacrificial film to provide a planarized second interlevel insulating film directly contacting said underlying second level wiring structure.

9 more elements

A method of manufacturing a semiconductor device with multi-layer wiring, the method comprising the steps of:

(a) providing an underlying structure of a semiconductor substrate having a first level wiring structure having a first thickness thereon;
(b) forming a first interlevel insulating film directly over the underlying structure having conformal topography to the underlying structure, the first interlevel insulating film having a second thickness thicker than said first thickness and having a first convex portion having a first width and a first concave portion having a second width wider than the first width;
(c) forming a first sacrificial film over the first interlevel insulating film having non-conformal topography to the first interlevel insulating film, the first concave portion being filled with the first sacrificial film, wherein said forming the first sacrificial film over the first interlevel insulating film includes:
(c-1) forming a first sacrificial sublayer over the first interlevel insulating film, the first sacrificial layer including silanol-based organic spin-on-glass;
and
(c-2) forming a second sacrificial sublayer over the first sacrificial sublayer to provide a laminated structure of the first and second sublayers, the second sacrificial layer including inorganic spin-on-glass;
(d) chemical-mechanical polishing the first interlevel insulating film having a second thickness thicker than said first thickness and the first sacrificial film to provide a planarized first interlevel insulating film;
(e) forming a second level wiring structure having a third thickness on the planarized first insulating film;
(f) forming a second intelevel insulating film directly over the second level wiring structure having conformal topography to the second level wiring structure, the second interlevel insulating film having a fourth thickness thicker than said third thickness and having a second convex portion having a third width and a second concave portion having a fourth width wider than the third width;
(g) forming a second sacrificial film, having non-conformal topography to the second interlevel insulating film, the second concave portion being filled with the second sacrificial film;
and
(h) chemical-mechanical polishing the second interlevel insulating film having said fourth thickness thicker than said third thickness and the second sacrificial film to provide a planarized second interlevel insulating film.

9 more elements

A method of manufacturing a semiconductor device with multi-layer wiring, the method comprising the steps of:

(a) providing an underlying structure of a semiconductor substrate having a first level wiring structure having a first thickness thereon;
(b) forming a first interlevel insulating film directly over the underlying structure having conformal topography to the underlying structure, the first interlevel insulating film having a second thickness thicker than said first thickness and having a first convex portion having a first width and a first concave portion having a second width wider than the first width;
(c) forming a first sacrificial film over the first interlevel insulating film having non-conformal topography to the first interlevel insulating film, the first concave portion being filled with the first sacrificial film;
(d) chemical-mechanical polishing the first interlevel insulating film having a second thickness thicker than said first thickness and the first sacrificial film to provide a planarized first interlevel insulating film;
(e) forming a second level wiring structure having a third thickness on the planarized first insulating film;
(f) forming a second interlevel insulating film directly over the second level wiring structure having conformal topography to the second level wiring structure, the second interlevel insulating film having a fourth thickness thicker than said third thickness and having a second convex portion having a third width and a second concave portion having a fourth width wider than the third width;
(g) forming a second sacrificial film, having non-conformal topography to the second interlevel insulating film, the second concave portion being filled with the second sacrificial film, wherein said forming the second sacrificial film includes:
(g-1) forming a first sacrificial sublayer over the second interlevel insulating film, the first sacrificial sublayer including silanol-based organic spin-on-glass;
and
(g-2) forming a second sacrificial sublayer over the first sacrificial sublayer to provide a laminated structure of the first and second sublayers, the second sacrificial sublayer including inorganic spin-on-glass;
and
(h) chemical-mechanical polishing the second interlevel insulating film having said fourth thickness thicker than said third thickness and the second sacrificial film to provide a planarized second interlevel insulating film.

9 more elements

A method of manufacturing a semiconductor device with multi-layer wiring, the method comprising the steps of:

(a) providing an underlying structure of a semiconductor substrate having a first level wiring structure thereon;
(b) forming a first interlevel insulating film over the underlying structure having conformal topography to the underlying structure;
(c) forming a first sacrificial sublayer of a first material for a first sacrificial film over the first interlevel insulating film;
(d) forming a second sacrificial sublayer of a second material different from said first material for said first sacrificial film over the first sacrificial sublayer to provide a laminated structure of said first sacrificial film having non-conformal topography to the first insulating film and having a substantially planar upper surface;
(e) chemical-mechanical polishing the first interlevel insulating film and the laminated structure of the first sacrificial film to provide a planarized first interlevel insulating film;
(f) forming a second level wiring structure on the planarized first interlevel insulating film;
(g) forming a second interlevel insulating film over the second level wiring structure having conformal topography to the second level wiring structure;
(h) forming a third sacrificial sublayer of a third material for a second sacrificial film over the second interlevel insulating film;
(i) forming a fourth sacrificial sublayer of a fourth material different from said third material for said second sacrificial film over the third sacrificial sublayer to provide a laminated structure of said second sacrificial film having non-conformal topography to the second interlevel insulating film and having a substantially planar upper surface;
and
(j) chemical-mechanical polishing the second interlevel insulating film and the laminated structure of the second sacrificial film to provide a planarized second interlevel insulating film.

8 more elements

Dependencies are inferred from the claim text.

Facts

Application

08/605,709Filed 22 Feb 1996 · continuation

Priority

JP 5-11785921 Apr 1993

Granted

6 Jan 1998

Term ends

Not estimatedThe source records don’t support an estimate.

Classification5 codes

H10P 95/06
Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass: planarisation of inorganic…
H10P 95/062
Planarisation of inorganic insulating materials: involving a dielectric removal step
H10W 20/092
Of dielectric parts thereof: by smoothing the dielectric parts
H10P
Generic processes or apparatus for the manufacture or treatment of devices covered

Abstract

Claims31

Dependent claims

A method of manufacturing a semiconductor device with multi-layer wiring, the method comprising the steps of:

(a) providing a semiconductor substrate having a first level wiring structure thereon;
(b) forming a second level wiring structure on the first level wiring structure;
(c) forming an interlevel insulating film on the second level wiring structure, the interlevel insulating film having a corrugated surface, the interlevel insulating film directly contacting said second level wiring structure;
(d) forming a sacrificial film over the interlevel insulating film, said sacrificial film having non-conformal topography to the underlying interlevel insulating film to form a planar upper surface on the semiconductor device, wherein said forming the sacrificial film over the interlevel insulating film includes:
(d-1) forming a first sacrificial sublayer over the interlevel insulating film directly contacting said second level wiring structure, the first sacrificial sublayer including silanol-based organic spin-on-glass;
and
(d-2) forming a second sacrificial sublayer over the first sacrificial sublayer to provide a laminated structure of the first and second sacrificial sublayers, the second sacrificial sublayer including inorganic spin-on-glass;
and
(e) chemical-mechanical polishing the interlevel insulating film directly contacting said second level wiring structure and the sacrificial film to provide a planarized interlevel insulating film directly contacting said second level wiring structure.

6 more elements

A method of manufacturing a semiconductor device with multi-layer wiring, the method comprising the steps of:

(a) providing an underlying structure of a semiconductor substrate having a first level wiring structure thereon;
(b) forming a first interlevel insulating film over the underlying structure having conformal topography to the underlying structure, said first interlevel insulating film directly contacting said underlying first level wiring structure;
(c) forming a first sacrificial film over the first insulating film, said first sacrificial film having non-conformal topography to the first insulating film and having a substantially planar upper surface, wherein said forming the first sacrificial film over the first insulating film includes:
(c-1) forming a first sacrificial sublayer over the first interlevel insulating film directly contacting said underlying first wiring structure, the first sacrificial sublayer including silanol-based organic spin-on-glass;
and
(c-2) forming a second sacrificial sublayer over the first sacrificial sublayer to provide a laminated structure of the first and second sublayers, the second sacrificial sublayer including inorganic spin-on-glass;
(d) chemical-mechanical polishing the first interlevel insulating film directly contacting said underlying first level wiring structure and the first sacrificial film to provide a planarized first interlevel insulating film directly contacting said underlying first level wiring structure;
(e) forming a second level wiring structure on the planarized first interlevel insulating film;
(f) forming a second interlevel insulating film over the second level wiring structure having conformal topography to the second level wiring structure, said second interlevel insulating film directly contacting said underlying second level wiring structure;
(g) forming a second sacrificial film over the second interlevel insulating film, said second sacrificial film having non-conformal topography to the second interlevel insulating film and having a substantially planar upper surface;
and
(h) chemical-mechanical polishing the second interlevel insulating film directly contacting said underlying second level wiring structure and the second sacrificial film to provide a planarized second interlevel insulating film directly contacting said underlying second level wiring structure.

9 more elements

A method of manufacturing a semiconductor device with multi-layer wiring, the method comprising the steps of:

(a) providing an underlying structure of a semiconductor substrate having a first level wiring structure thereon;
(b) forming a first interlevel insulating film over the underlying structure having conformal topography to the underlying structure, said first interlevel insulating film directly contacting said underlying first level wiring structure;
(c) forming a first sacrificial film over the first insulating film, said first sacrificial film having non-conformal topography to the first insulating film and having a substantially planar upper surface;
(d) chemical-mechanical polishing the first interlevel insulating film directly contacting said underlying first level wiring structure and the first sacrificial film to provide a planarized first interlevel insulating film directly contacting said underlying first level wiring structure:
(e) forming a second level wiring structure on the planarized first interlevel insulating film;
(f) forming a second interlevel insulating film over the second level wiring structure having conformal topography to the second level wiring structure, said second interlevel insulating film directly contacting said underlying second level wiring structure;
(g) forming a second sacrificial film Over the second interlevel insulating film, said second sacrificial film having non-conformal topography to the second interlevel insulating film and having a substantially planar upper surface, wherein said forming the second sacrificial film over the second interlevel insulating film includes:
(g-1) forming a first sacrificial sublayer over the second interlevel insulating film directly contacting said underlying second level wiring structure, the first sacrificial sublayer including silanol-based organic spin-on-glass;
and
(g-2) forming a second sacrificial sublayer over the first sacrificial sublayer to provide a laminated structure of the first and second sublayers, the second sacrificial sublayer including inorganic spin-on-glass;
and
(h) chemical-mechanical polishing the second interlevel insulating film directly contacting said underlying second level wiring structure and the second sacrificial film to provide a planarized second interlevel insulating film directly contacting said underlying second level wiring structure.

9 more elements

A method of manufacturing a semiconductor device with multi-layer wiring, the method comprising the steps of:

(a) providing an underlying structure of a semiconductor substrate having a first level wiring structure having a first thickness thereon;
(b) forming a first interlevel insulating film directly over the underlying structure having conformal topography to the underlying structure, the first interlevel insulating film having a second thickness thicker than said first thickness and having a first convex portion having a first width and a first concave portion having a second width wider than the first width;
(c) forming a first sacrificial film over the first interlevel insulating film having non-conformal topography to the first interlevel insulating film, the first concave portion being filled with the first sacrificial film, wherein said forming the first sacrificial film over the first interlevel insulating film includes:
(c-1) forming a first sacrificial sublayer over the first interlevel insulating film, the first sacrificial layer including silanol-based organic spin-on-glass;
and
(c-2) forming a second sacrificial sublayer over the first sacrificial sublayer to provide a laminated structure of the first and second sublayers, the second sacrificial layer including inorganic spin-on-glass;
(d) chemical-mechanical polishing the first interlevel insulating film having a second thickness thicker than said first thickness and the first sacrificial film to provide a planarized first interlevel insulating film;
(e) forming a second level wiring structure having a third thickness on the planarized first insulating film;
(f) forming a second intelevel insulating film directly over the second level wiring structure having conformal topography to the second level wiring structure, the second interlevel insulating film having a fourth thickness thicker than said third thickness and having a second convex portion having a third width and a second concave portion having a fourth width wider than the third width;
(g) forming a second sacrificial film, having non-conformal topography to the second interlevel insulating film, the second concave portion being filled with the second sacrificial film;
and
(h) chemical-mechanical polishing the second interlevel insulating film having said fourth thickness thicker than said third thickness and the second sacrificial film to provide a planarized second interlevel insulating film.

9 more elements

A method of manufacturing a semiconductor device with multi-layer wiring, the method comprising the steps of:

(a) providing an underlying structure of a semiconductor substrate having a first level wiring structure having a first thickness thereon;
(b) forming a first interlevel insulating film directly over the underlying structure having conformal topography to the underlying structure, the first interlevel insulating film having a second thickness thicker than said first thickness and having a first convex portion having a first width and a first concave portion having a second width wider than the first width;
(c) forming a first sacrificial film over the first interlevel insulating film having non-conformal topography to the first interlevel insulating film, the first concave portion being filled with the first sacrificial film;
(d) chemical-mechanical polishing the first interlevel insulating film having a second thickness thicker than said first thickness and the first sacrificial film to provide a planarized first interlevel insulating film;
(e) forming a second level wiring structure having a third thickness on the planarized first insulating film;
(f) forming a second interlevel insulating film directly over the second level wiring structure having conformal topography to the second level wiring structure, the second interlevel insulating film having a fourth thickness thicker than said third thickness and having a second convex portion having a third width and a second concave portion having a fourth width wider than the third width;
(g) forming a second sacrificial film, having non-conformal topography to the second interlevel insulating film, the second concave portion being filled with the second sacrificial film, wherein said forming the second sacrificial film includes:
(g-1) forming a first sacrificial sublayer over the second interlevel insulating film, the first sacrificial sublayer including silanol-based organic spin-on-glass;
and
(g-2) forming a second sacrificial sublayer over the first sacrificial sublayer to provide a laminated structure of the first and second sublayers, the second sacrificial sublayer including inorganic spin-on-glass;
and
(h) chemical-mechanical polishing the second interlevel insulating film having said fourth thickness thicker than said third thickness and the second sacrificial film to provide a planarized second interlevel insulating film.

9 more elements

A method of manufacturing a semiconductor device with multi-layer wiring, the method comprising the steps of:

(a) providing an underlying structure of a semiconductor substrate having a first level wiring structure thereon;
(b) forming a first interlevel insulating film over the underlying structure having conformal topography to the underlying structure;
(c) forming a first sacrificial sublayer of a first material for a first sacrificial film over the first interlevel insulating film;
(d) forming a second sacrificial sublayer of a second material different from said first material for said first sacrificial film over the first sacrificial sublayer to provide a laminated structure of said first sacrificial film having non-conformal topography to the first insulating film and having a substantially planar upper surface;
(e) chemical-mechanical polishing the first interlevel insulating film and the laminated structure of the first sacrificial film to provide a planarized first interlevel insulating film;
(f) forming a second level wiring structure on the planarized first interlevel insulating film;
(g) forming a second interlevel insulating film over the second level wiring structure having conformal topography to the second level wiring structure;
(h) forming a third sacrificial sublayer of a third material for a second sacrificial film over the second interlevel insulating film;
(i) forming a fourth sacrificial sublayer of a fourth material different from said third material for said second sacrificial film over the third sacrificial sublayer to provide a laminated structure of said second sacrificial film having non-conformal topography to the second interlevel insulating film and having a substantially planar upper surface;
and
(j) chemical-mechanical polishing the second interlevel insulating film and the laminated structure of the second sacrificial film to provide a planarized second interlevel insulating film.

8 more elements

Dependencies are inferred from the claim text.

Method of manufacturing a semiconductor device with flattened multi-layer wirings

Life of this patent

Abstract

Claims31

Method of manufacturing a semiconductor device with flattened multi-layer wirings

Life of this patent

Abstract

Claims31