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US 5,703,387 AGranted
Split gate memory cell with vertical floating gate
AssigneeUnited Microelectronics Corp.
InventorGary Hong
Life of this patent
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Abstract
A vertical split gate memory device has a semiconductor substrate with a trench and a floating gate formed on a sidewall of the trench, thus reducing the surface area of each memory cell. The fabrication process for this device allows precise control over the consistency during fabrication because the length of the floating gate is controlled by the depth of a trench etch and the location of the drains and sources are self-aligned by oxide spacers which act as masks during the doping process.
Claims11
A split gate memory device, comprising:
- a) a semiconductor substrate of a first conductivity type having a surface and a trench having a bottom surface, sidewalls, and top formed therein;
- b) a first heavily doped region of semiconductor material formed in the substrate surface having a second conductivity type opposite to said first conductivity type;
- c) a second heavily doped region of semiconductor material formed in said substrate at the bottom surface of said trench and having the second conductivity type, the second region configured to form part of a bitline, each of said first and second regions forming either one of a drain and a source;
- d) a floating gate formed on a sidewall of the trench;
- and
- e) a control gate formed generally perpendicular to the floating gate and above the substrate surface and above and across the top of the trench.
3 more elements
Dependencies are inferred from the claim text.