Semiconductor integrated circuit

A semiconductor integrated circuit comprising:

• a semiconductor substrate having an area in which an integrated circuit is formed;
• a PMOS transistor of a circuit formed in said semiconductor substrate of the circuit forming area of the integrated circuit having a first source region formed of a first impurity diffusion layer, a first drain region, and a first gate electrode;
• an NMOS transistor of said circuit formed in said semiconductor substrate of the circuit forming area of the integrated circuit having a second source region formed of a second impurity diffusion layer, a second drain region, and a second gate electrode;
• a PMOS transistor of a test element sharing said first source region formed of the first impurity diffusion layer with said PMOS transistor of said circuit and having a third drain region and a third gate electrode;
• and
• an NMOS transistor of a test element sharing said second source region formed of the second impurity diffusion layer with said NMOS transistor of said circuit and having a fourth drain region and a fourth gate electrode;
• a first test pad connected to the third gate electrode of said PMOS transistor of said test element;
• a second test pad connected to the third drain region of said PMOS transistor of said test element;
• a third test pad connected to the fourth gate electrode of said NMOS transistor of said test element;
• and
• a fourth test pad connected to the fourth drain region of said NMOS transistor of said test element;
• said pMOS and NMOS transistors of said circuit constituting a CMOS inverter circuit which has an input terminal connected to the first and second gate electrodes and an output terminal connected to the first and second drain regions, the first source region commonly used by said PMOS transistor of said test element being connected to the power supply terminal and the second source region commonly used by said NMOS transistor of said test element being connected to reference potential terminal.