Method for fabricating a tub structured stacked capacitor for a DRAM cell having a central column

A method of fabricating a dynamic random access memory cell having an tub structured capacitor with a central column on a substrate, comprising the steps of:

• a) forming a MOS (metal oxide semiconductor) device, having source and drain regions, adjacent to a field oxide region in a silicon substrate;
• b) forming a conductive word line over said field oxide region;
• c) forming an etch barrier layer over said substrate, including said MOS device, said word line, and said field oxide region;
• d) forming a first insulating layer over said etch barrier layer;
• e) planarizing said first insulating layer by a chemical mechanical polishing process;
• f) forming a first resist layer over said first insulating layer;
• said first resist layer having an first opening over said source region;
• g) anisotropically etching said first insulating layer through said first opening forming a contact hole exposing portions of said source region;
• h) removing said first resist layer;
• i) forming a first conductive layer over said first insulating layer and filling said contact hole thereby forming an electrical contact to said source region;
• j) chemically mechanically polishing said first conductive layer over said first insulating layer to a depth that at least exposes said first insulating layer thereby forming a central vertical extension;
• k) forming a second resist layer over said first insulating layer;
• said second resist layer having an opening over an area where a storage electrode will be formed;
• l) anisotropically etching said first insulating layer using the second resist layer as a mask thereby forming a trench surrounding said central vertical extension;
• said trench having vertical sidewalls;
• m) forming a second conductive layer over said trench, said central vertical extension, and said first insulating layer;
• n) forming an dielectric layer over said second conductive layer and filling said trench;
• o) chemically mechanically polishing said dielectric layer, said second conductive layer, and said central vertical extension to a depth that at least exposes said first insulating layer thereby forming a storage electrode;
• p) removing said first insulating layer and said dielectric layer;
• and
• q) sequentially forming a capacitor dielectric layer and a top electrode over said at least said storage electrode thereby forming said tub structured capacitor having said central column.