Method of manufacture of self-aligned JFET

A method of forming a junction field effect transistor device by the steps comprising:

• starting with a semiconductor substrate with a <110>
• crystallographic orientation doped with a first conductivity type of dopant to form a drain region having a top surface and a bottom surface,
• said substrate being coated on said top surface with an epitaxial semiconductor layer having a <110>
• crystallographic orientation, said epitaxial semiconductor layer being doped in a lesser concentration than said drain region with said first conductivity type of dopant to provide an active region for said junction field effect device, said epitaxial layer having an exposed surface,
• doping the surface of said epitaxial layer with an additional amount of said first conductivity type of dopant to provide a source region layer on the surface of said epitaxial layer,
• forming first and second masking material layers on said source region layer,
• forming a mask with mask openings therethrough over said first and second masking material layers, and forming patterned openings in said masking material through said mask openings, and removing said mask from over said first and second masking material layers,
• trench etching to form a plurality of gate trenches through said patterns in said masking material layers and said source region layer forming source regions in said source region layer, and continuing said trench etching with said gate trenches extending partially through said epitaxial layer, said trenches having sidewalls and bottoms,
• said trench etching comprising etching through said source region layer and said epitaxial layer along a {111} crystallographic plane,
• forming a dielectric spacer layer over said sidewalls and bottoms of said gate trenches upon exposed portions of said source region layer and said epitaxial layer in said gate trenches,
• etching away said spacer layer from said bottoms of said gate trenches through said patterned openings in said masking material and etching below said bottoms deepening said trenches,
• forming a plurality of gate regions with one gate region at the each of the bottoms of each of said gate trenches in said epitaxial layer by doping thereof by diffusion,
• removing said masking material layers, and
• forming electrodes upon exposed surfaces of said source regions, said gate regions and said drain region.

A method of forming a junction field effect transistor device by the steps comprising:

• starting with a semiconductor substrate with a <110>
• crystallographic orientation doped with a first conductivity type of dopant to form a drain region having a top surface and a bottom surface,
• said substrate being coated on said top surface with an epitaxial semiconductor layer having a <110>
• crystallographic orientation, said epitaxial semiconductor layer being about 40 .mu.m thick,
• said epitaxial semiconductor layer being doped with a doping concentration of from about 1 E 14 atoms/cm.sup.3 to about 5 E 14 atoms/cm.sup.3,
• said doping concentration being less than the doping concentration in said drain region with said first conductivity type of dopant to provide an active region for said junction field effect device,
• said epitaxial layer having an exposed surface,
• doping the surface of said epitaxial layer with an additional amount of said first conductivity type of dopant to provide a source region layer on the surface of said epitaxial layer with a doping concentration from about 1 E 19 atoms/cm.sup.3 to about 1 E 20 atoms/cm.sup.3,
• forming first and second masking material layers on said source region layer composed of a silicon nitride lower masking material layer below a silicon dioxide upper masking material layer,
• forming a mask with openings therethrough over said first and second masking material layers and forming patterns in said first and second masking material layers through said openings,
• trench etching in an orientation etch performed along the {111} crystallographic plane to form a plurality of gate trenches through said masking material layers and said source region layer forming source regions in said source region layer, and continuing said trench etching with said gate trenches extending partially through said epitaxial layer, said trenches having sidewalls and bottoms,
• said trench etching comprising etching through said source region layer and said epitaxial layer along said {111} crystallographic plane providing vertically extending sidewalls,
• forming a dielectric spacer layer over said sidewalls and bottoms of said gate trenches upon exposed portions of said source region layer and said epitaxial layer in said gate trenches,
• etching away said spacer layer from said bottoms of said gate trenches,
• forming a plurality of gate regions with one gate region at the each of the bottoms of each of said gate trenches in said epitaxial layer by doping thereof by diffusion,
• removing said masking material layers, and
• forming electrodes upon exposed surfaces of said source regions, said gate regions and said drain region.

A method of forming a junction field effect transistor device by the steps comprising

• starting with a semiconductor substrate with a <110>
• crystallographic orientation doped with a N+ conductivity type of dopant to form a drain region having a top surface and a bottom surface,
• said substrate being coated on said top surface with an epitaxial semiconductor layer having a <110>
• crystallographic orientation,
• said epitaxial semiconductor layer being about 40 .mu.m thick,
• said epitaxial semiconductor layer being doped with a N- conductivity type of dopant doping concentration of from about 1 E 14 atoms/cm.sup.3 to about 5 E 14 atoms/cm.sup.3, said doping concentration being less than said drain region with said first conductivity type of dopant to provide an active region for said junction field effect device,
• said epitaxial layer having an exposed surface,
• doping the surface of said epitaxial layer with an additional amount of said N conductivity type of dopant to provide a source region layer on the surface of said epitaxial layer with a doping concentration of from about 1 E 19 atoms/cm.sup.3 to about 1 E 20 atoms/cm.sup.3,
• forming first and second masking layers on said source region layer composed of a silicon nitride lower masking layer below a silicon dioxide upper masking layer,
• forming a mask with openings therethrough over said first and second masking layers and forming mask patterns in said masking layers through said openings,
• trench etching in an orientation etch performed along the {111} crystallographic plane with an etchant selected from the group consisting of an aqueous solution of KOH and a dry plasma etch to form a plurality of gate trenches through said mask openings in said masking layers and said source region layer forming source regions in said source region layer, and continuing said trench etching with said gate trenches extending partially through said epitaxial layer, said trenches having vertically extending sidewalls comprising exposed portions of said source region layer and said epitaxial layer and having bottoms below said sidewalls,
• forming a dielectric spacer layer with a thickness from about 800 .ANG. to about 1,200 .ANG. by forming a thermal oxide on said sidewalls and the said bottoms of said gate trenches,
• etching away said spacer layer from said bottoms of said gate trenches, etching away said silicon dioxide upper masking layer with a dry anisotropic RIE etchant gas,
• etching said N-doped epitaxial layer with CF.sub.4 gas to provide an overall depth of said trenches from about 10 .mu.m to about 16 .mu.m,
• forming a plurality of gate electrode regions with one gate region at the each of the bottoms of each of said gate trenches doped by diffusion of P+ boron (B.sup.11) into said epitaxial layer,
• removing said masking layers, and
• forming contacts upon exposed surfaces of said source regions, said gate electrode regions and said drain region.