Low-stress method of fabricating field-effect transistors having silicon nitride spacers on gate electrode edges

A process for forming an insulated-gate field-effect transistor on a silicon substrate, said process comprising the following steps:

• (a) growing a gate dielectric layer on the substrate;
• (b) depositing at least one conductive layer on top of the gate dielectric layer;
• (c) depositing an insulative layer on top of said at least one conductive layer;
• (d) forming a mask pattern on the insulative layer, said mask pattern having a profile which corresponds to that of a gate electrode;
• (e) anisotropically etching through both the insulative layer and the conductive layer to form a gate electrode having a insulative layer portion, a conductive layer portion and sidewalls formed from both the edges of the insulative layer portion and the conductive layer portion;
• (f) depositing a conformal silicon nitride layer which overlies the substrate and covers the sidewalls and the insulative layer portion;
• (g) depositing a conformal silicon dioxide layer which covers the conformal silicon nitride layer;
• (h) performing an anisotropic etch to form spacers from the silicon dioxide layer and the silicon nitride layer on each of the sidewalls, each spacer having both a silicon nitride portion and a silicon dioxide portion;
• (i) performing a source/drain implant with at least the silicon nitride portion of the spacer on the sidewalls;
• and
• (j) performing a post-implant anneal with only the silicon nitride portion of the spacer on the sidewalls.

A process for mitigating stress-induced damage to a silicon substrate during post-implant annealing of source/drain regions of a field-effect transistor, said transistor having a gate electrode which has been formed on the substrate, said electrode having sidewalls which are approximately normal to the substrate, said electrode also having an upper surface that is covered by an insulative layer, said process comprising the steps of:

• (a) depositing a conformal silicon nitride layer which covers the substrate, the sidewalls and the insulative layer;
• (b) depositing a conformal silicon dioxide layer which covers the conformal silicon nitride layer;
• (c) performing an anisotropic etch which forms spacers on each of the sidewalls, each spacer having both a silicon nitride portion and a silicon dioxide portion;
• (d) removing the silicon dioxide portion of each spacer;
• (e) performing a post-implant anneal with only the silicon nitride portion of the spacer on the sidewalls.