US 5,702,982 AGranted

Method for making metal contacts and interconnections concurrently on semiconductor integrated circuits

AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.

InventorsChung-Kuang Lee, Jung-Hsien Hsu, Pin-Nan Tseng

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Abstract

A method for making metal interconnections and buried metal plug structures for multilevel interconnections on semiconductor integrated circuits was achieved. The method utilizes a single patterned photoresist layer for etching trenches in an insulating layer, while at the same time protecting the device contact areas in the contact openings from being etched, thereby reducing process complexity and manufacturing cost. After the trenches are formed, the patterned photoresist layer and the photoresist in the contact openings is removed by plasma ashing, and a metal layer is deposited and etched back or chem/mech polished to form concurrently the metal interconnections and the buried metal plug contacts. The surface of the metal interconnections is coplanar with the insulating surface, thereby allowing the process to be repeated several times to complete the necessary multilevel of metal wiring needed to wire-up the integrated circuits while maintaining a planar surface.

Claims32

Dependent claims

A method for fabricating electrical interconnection and buried metal plug structures, concurrently, on a semiconductor substrate, comprising the steps of:

providing a semiconductor substrate having device areas and field oxide areas, and further having semiconductor devices in said device areas with device contact areas;
depositing a blanket insulating layer composed of an inorganic material on said semiconductor device areas, said insulating layer having a planar surface over said substrate;
masking and anisotropically plasma etching contact openings in said insulating layer to said device contact areas;
coating a photoresist layer on said insulating layer and filling said contact openings, said photoresist layer having a planar surface over said contact openings;
patterning said photoresist layer on said insulating layer and forming a photoresist etch mask for etching trenches in said insulating layer extending over said contact openings, and leaving a portion of said photoresist layer in said contact openings;
anisotropically plasma etching said trenches extending partially into said insulating layer, said photoresist in said contact openings protecting said device contact areas from being etched;
plasma ashing and thereby completely removing said patterned photoresist layer and portions of said photoresist in said contact openings;
depositing a conformal metal layer, and filling said trenches and said contact openings in said insulating layer, said metal layer deposited to a thickness that forms a planar surface over said trenches;
blanket removing said metal layer to the surface of said insulating layer, and thereby leaving metal in said trenches and in said contact openings, said metal in said trenches and in said contact openings being coplanar with the surface of said insulating layer, and thereby completing said electrical interconnections and metal plug structures.

6 more elements

A method for fabricating electrical interconnection and buried metal plug structures, concurrently, on a semiconductor substrate, comprising the steps of:

providing a semiconductor substrate having device areas and field oxide areas, and further having semiconductor devices in said device areas with device contact areas;
depositing a blanket insulating layer composed of an inorganic material on said semiconductor device areas, said insulating layer composed of silicon oxide and having a planar surface over said substrate;
masking and anisotropically plasma etching contact openings in said insulating layer to said device contact areas;
coating a photoresist layer on said insulating layer and filling said contact openings, said photoresist layer having a planar surface over said contact openings;
patterning said photoresist layer on said insulating layer and forming a photoresist etch mask for etching trenches in said insulating layer extending over said contact openings, and leaving a portion of said photoresist layer in said contact openings;
anisotropically plasma etching said trenches extending partially into said insulating layer, said photoresist layer in said contact openings protecting said device contact areas from being etched;
plasma ashing and thereby completely removing said patterned photoresist layer and portions of said photoresist in said contact openings;
depositing a conformal metal layer, and filling said trenches and said contact openings in said insulating layer, said conformal metal layer deposited to a thickness that forms a planar surface over said trenches;
plasma etching back said conformal metal layer to the surface of said insulating layer, and thereby leaving metal in said trenches and in said contact openings, said metal in said trenches and in said contact openings being coplanar with the surface of said insulating layer, and thereby completing said electrical interconnection and buried metal plug structures.

6 more elements

A method for fabricating multilevel electrical interconnections and buried metal plug structures for integrated circuits on a semiconductor substrate, comprising the steps of:

(a) providing a semiconductor substrate having device areas and field oxide areas, and further having semiconductor devices in said device areas;
(b) depositing a blanket insulating layer composed of an inorganic material on said semiconductor device areas, said insulating layer having a planar surface over said substrate;
(c) masking and anisotropically plasma etching contact openings in said insulating layer to contact areas on said substrate;
(d) coating a photoresist layer on said insulating layer and filling said contact openings, said photoresist layer having a planar surface over said contact openings;
(e) patterning said photoresist layer on said insulating layer and forming a photoresist etch mask for etching trenches in said insulating layer extending over said contact openings, and leaving a portion of said photoresist layer in said contact openings;
(f) anisotropically plasma etching said trenches extending partially into said insulating layer, said photoresist left in said contact openings protecting said contact areas from being etched;
(g) plasma ashing, and thereby completely removing said patterned photoresist layer and portions of said photoresist in said contact openings;
(h) depositing a conformal metal layer, and filling said trenches and said contact openings in said insulating layer, said metal layer having a planar surface;
(i) blanket removing said metal layer to the surface of said insulating layer, and thereby leaving metal in said trenches and in said contact openings, said metal in said trenches and in said contact openings being coplanar with the surface of said insulating layer, and thereby completing said electrical interconnections and buried metal plug structures;
and further, forming additional levels of electrical interconnections and buried metal plugs by;
(j) depositing another insulating layer composed of an inorganic material;
(k) etching contact openings in said other insulating layer to said patterned metal layer in said trenches in said insulating layer;
(l) repeating steps (d) through (i) and thereby forming another level of electrical interconnections and buried metal plug structures;
(m) repeating steps (j) through (1) for each additional level of interconnections required to complete said multilevel electrical interconnections and buried metal plug structures for said integrated circuits.

11 more elements

Dependencies are inferred from the claim text.