Shallow trench isolation method employing self-aligned and planarized trench fill dielectric layer

A method for forming and planarizing a trench fill dielectric layer within an isolation trench within an integrated circuit comprising:

• providing a substrate, the substrate having an isolation trench formed therein;
• forming upon the substrate at regions other than those within the isolation trench a first integrated circuit layer, the first integrated circuit layer having a composition which inhibits formation upon the first integrated circuit layer of a trench fill dielectric layer which is subsequently formed upon the substrate and within the isolation trench;
• forming within the isolation trench but not upon the substrate at regions other than those within the isolation trench a second integrated circuit layer, the second integrated circuit layer having a composition which promotes formation within the isolation trench of the trench fill dielectric layer which is subsequently formed upon the substrate and within the isolation trench;
• and
• forming upon the substrate and within the isolation trench the trench fill dielectric layer, the trench fill dielectric layer being formed to a thickness over the isolation trench such that when the trench fill dielectric layer is planarized through a chemical mechanical polish (CMP) planarizing method there is avoided formation of a dish within a planarized trench fill dielectric layer formed within the isolation trench.