Method for fabricating a honeycomb shaped capacitor

A method of fabricating a honeycomb shaped capacitor comprising the steps of:

• forming a first planarization layer over a substrate surface;
• etching a node contact hole though said first planarization layer exposing a source;
• forming a first polysilicon layer on said first planarization layer and in said node contact hole;
• forming a first insulation layer over said first conductive layer;
• said first insulating composed of a material selected from the group consisting of silicon oxide and borophosphosilicate glass;
• and has a thickness in a range between about 4000 and 7000 .ANG.;
• forming a hemisphere particle layer over said first insulation layer;
• said hemisphere particle layer comprises grains having a diameter in a range between about 500 and 1500 .ANG.;
• said hemisphere particle layer is formed by depositing a conformal polysilicon layer over said first insulation layer and annealing said conformal polysilicon layer;
• said conformal polysilicon layer is deposited using He-diluted SiH.sub.4 at a percentage between about 10 and 30%;
• at a pressure in a range between about 0.5 and 2 Torr;
• and at a temperature in a range between about 550.degree. to 590.degree. C.:
• said annealing comprises a two step anneal process;
• a first step has an oxygen partial pressure in a range between about 1E-5 and 5E-5 Torr for a time in a range between about 30 and 90 seconds and a temperature in a range between about 550.degree. and 590.degree. C.;
• and a second step having an oxygen partial pressure in a range between about 1E-7 and 3E-7 Torr for a time in a range between about 20 and 40 minutes and a temperature in a range between about 550.degree. and 590.degree. C.;
• anisotropically etching said first insulation layer using said hemisphere particle layer as a mask forming pattern of vertical extensions of said first insulation layer;
• said vertical extensions having a diameter in a range of between about 0.05 and 0.15 .mu.m and a height in a range of between about 0.4 and 0.7 .mu.m and a spacing between the vertical extensions in a range of between about 0.05 and 0.15 .mu.m;
• forming a third polysilicon layer over said hemisphere particle layer and said pattern of vertical extensions;
• etching back said third polysilicon layer and said hemisphere particle layer to expose the tops of said vertical extensions of said first insulation layer;
• selectively etching said vertical extensions of said first insulation layer forming holes in place of said vertical extensions in said third polysilicon layer thereby forming said third polysilicon layer into a honeycomb structure;
• patterning said first polysilicon layer and said third polysilicon layer forming a honeycomb shaped bottom storage electrode over said source;
• forming a capacitor dielectric layer over said bottom storage electrode;
• and
• forming a top plate electrode over said capacitor dielectric layer thereby forming said honeycomb shaped capacitor.

A method of fabricating a honeycomb shaped capacitor for a memory device comprising:

• forming a first planarization layer over a substrate surface;
• said first planarization layer is composed of a material selected from the group consisting of silicon oxide and borophosphosilicate glass;
• and has a thickness in a range between about 3000 and 7000 .ANG.;
• etching a node contact hole though said first planarization layer exposing a source;
• forming a first polysilicon layer superjacent said first planarization layer and in said node contact hole;
• said first polysilicon layer is formed of doped polysilicon having an impurity concentration in a range between about 1E 19 and 1E 20 atoms/cm.sup.3 and a thickness in a range between about 2000 and 3000 .ANG.;
• forming a first insulation layer over said first polysilicon layer;
• said first insulation layer is composed of a material selected from the group consisting of silicon oxide and borophosphosilicate glass;
• and has a thickness in a range between about 4000 and 7000 .ANG.;
• forming a conformal polysilicon layer over said first insulation layer;
• and annealing said conformal polysilicon layer in a partial oxygen ambient thereby forming a hemisphere particle layer over said first insulation layer;
• said hemisphere particle layer comprises grains having a diameter in a range between about 500 and 1500 .ANG.;
• said hemisphere particle layer, is formed by depositing a conformal polysilicon layer over said first insulation layer;
• and annealing said conformal polysilicon layer;
• and
• said conformal polysilicon layer is deposited using He-diluted SiH.sub.4 at a percentage between about 10 and 30%;
• at a pressure in a range between about 0.5 and 2 Torr;
• and at a temperature in a range between about 550.degree. to 590.degree. C.;
• said annealing comprises a two step anneal process;
• a first step has an oxygen partial pressure in a range between about 1E-5 and 1.9E-5 Torr for a time in a range between about 30 and 90 seconds and a temperature in a range between about 550.degree. and 590.degree. C.;
• and a second step having an oxygen partial pressure in a range between about 2.6E-7 and 3.0E-7 Torr for a time in a range between about 20 and 40 minutes and a temperature in a range between about 550.degree. and 590.degree. C.;
• etching said hemisphere particle layer to decrease the diameter of said particles;
• anisotropically etching said first insulation layer using said hemisphere particle layer as a mask forming pattern of vertical extensions of said first insulation layer;
• said vertical extensions having a diameter in a range of between about 0.05 and 0.15 .mu.m and a height in a range of between about 0.4 and 0.7 .mu.m and a spacing between the vertical extensions in a range of between about 0.05 and 0.15 .mu.m;
• forming a third polysilicon layer over said hemisphere particle layer and said pattern of vertical extensions;
• said third polysilicon layer has a thickness in a range of between about 0.05 and 0.15 .mu.m and an impurity doping concentration in a range of between about 1E 19 and 1E 20 atoms/cm.sup.3 ;
• etching back said third polysilicon layer and said hemisphere particle layer to expose tops of said vertical extensions of said first insulation layer;
• selectively etching said vertical extensions of said first insulation layer forming holes in place of said vertical extensions in said first polysilicon layer thereby forming the third polysilicon layer into a honeycomb structure;
• patterning said first polysilicon layer and said third polysilicon layer forming a honeycomb shaped bottom storage electrode over said source;
• forming a capacitor dielectric layer over said bottom storage electrode;
• and
• forming a top plate electrode over said capacitor dielectric layer thereby forming said honeycomb shaped capacitor;
• said top plate electrode is formed of doped polysilicon having a thickness in a range between about 500.degree. and 1500 .ANG. and an impurity concentration in a range between about 1E19 and 1E 20 atoms/cm.sup.3.