US 5,702,956 A · Test site and a method of monitoring via etch depths for semiconductor devices

Abstract

The present invention provides a test site on a product wafer for measuring via etch depth and a method of monitoring the depth of the vias using the test site. A substrate is provided having a test site area and a circuit area. A test site via is formed in the test site area. The test site via is used in measuring the depth of the insulating layers remaining in a test site via and the depth of the test site via. The measurements are taking using an in-line non-destructible measurement tool, such as an ellipsometer or spectrophotometer. The test site is specifically designed to be large enough to have the via depth measured by an in-line measuring tool. The depth of the oxide remaining in the test site via is measured after the via etch and is correlated to the amount of titanium nitride removed from the tops of the metal lines in the circuit areas. The via etch process is then adjusted to center the via etch at the optimum point to ensure that enough the vias are deep enough without removing too much of the top barrier layer (e.g., titanium nitride) film over the metal lines.

Claims20

Dependent claims

A method of monitoring the via etch removal of a top barrier layer over a metal layer on a semiconductor substrate comprising:

a) providing a semiconductor substrate having at least a test site area and a circuit area;
b) forming field oxide regions and semiconductor elements over portions of said substrate in said test site area and said circuit area;
c) forming an interlevel dielectric layer over said field oxide regions and said semiconductor elements;
d) forming first metal lines having a top barrier layer over portions of said circuit area;
e) an intermetal dielectric layer over said metal lines and said interlevel dielectric layer;
f) etching a test site via through portions of said intermetal dielectric layer in said test site area and simultaneously etching circuit vias through at least portions of said inter metal dielectric layer in said circuit area over said metal lines;
and
g) measuring the thicknesses of said field oxide region, said interlevel dielectric layer and said intermetal dielectric layer under said test site via.

5 more elements

A method of monitoring via depth by forming a test site via in an intermetal dielectric layer and measuring the depth of said test site via, comprising;

a) providing a semiconductor substrate having at least a test site area and a circuit area;
said circuit area having a shallow via area and a deep via area;
b) forming field oxide regions in said test site area and said circuit area;
c) forming a polycide layer over portions of said field oxide regions in at least said shallow via area;
d) forming an interlevel dielectric (ILD) layer over the resultant surface;
e) forming first metal lines over said interlevel dielectric layer in said shallow via area and in said deep via area;
f) forming a top barrier layer composed of titanium nitride over said first metal lines;
g) forming an intermetal dielectric (IMD) layer over the resultant surface;
h) forming a via photoresist layer over said intermetal dielectric layer, said via photoresist layer having openings over said circuit area and said test site area;
i) etching portions of said inter metal dielectric layer and said top barrier layer using said via photoresist layer as a mask, forming at least a test site via in said test site area, forming a shallow via in said shallow via area, and forming a deep via in said deep via area;
j) measuring and correlating the depth of the test site via to the thickness of said top barrier layer in said circuit area removed by the etching in step (i).

8 more elements

Dependencies are inferred from the claim text.

Test site and a method of monitoring via etch depths for semiconductor devices

Life of this patent

Test site and a method of monitoring via etch depths for semiconductor devices

Life of this patent

Abstract

Claims20