Method for forming multi-layer interconnections

A method of forming a semiconductor device having a multi-layer interconnection in which through-holes are formed in an interlayer insulating layer positioned between two neighboring mid interconnection layers, which through-holes are used for establishing an electrical interconnection between upper and lower interconnection layers, comprising the steps of:

• forming an offset insulating film on said mid interconnection layer such that the patterns of the mid interconnection layer and the offset insulating film are the same;
• forming a sidewall insulating film on a lateral wall surface of a pattern made up of said mid interconnection layer and the offset insulating film;
• substantially conformally forming an etching stop layer covering the entire surface of the semiconductor device, said etching stop layer being slower in etch rate than said interlayer insulating layer;
• forming the insulating film so as to be substantially planer and so as to cover the entire surface of said semiconductor device for completing a through hole;
• and
• anisotropically etching said interlayer insulating layer in a region having an opening size smaller than the spacing between the interconnecting layers;
• selectively removing the etching stop layer exposed on the bottom surface of said region for completing the through-hole;
• and
• filling said through-hole with an electrically conductive material.