Method of fabricating a programmable polysilicon gate array base cell structure

A method of fabricating a gate array structure on a semiconductor substrate, the method comprising the following steps:

• forming an array of identical base cells in a core region of the structure, each such base cell having
• (a) a plurality of transistors, with each such transistor including a gate electrode, and
• (b) one or more gate connection strips electrically formed on said substrate and connecting selected gate electrodes of two or more of said transistors;
• and
• patterning the gate connection strips to maintain electrical connection between at least two of the selected gate electrodes,
• wherein said plurality of transistors includes (i) a first group of transistors of a first conductivity type, each having a first gate width, (ii) a second group of transistors of a second conductivity type, opposite said first conductivity type, each transistor of said second group having a second gate width that is substantially equal to the first gate width, and (iii) a third group of transistors of said first conductivity type, each having a third gate width which is smaller than the first and second gate widths, wherein the transistors of the first and second groups all have gates that are aligned in parallel with a first axis, and the transistors of the third group all have gates that are aligned in parallel with a second axis that is substantially perpendicular to the first axis.