Non-volatile semiconductor memory device with thin insulation layer below erase gate

A non-volatile semiconductor memory device comprising:

• first and second memory cells having floating gates formed on a substrate;
• an erasure gate electrode bridging between said first and second memory cells and holding a given potential upon injection of a charge into said floating gate electrode;
• and
• an isolation layer controlled by the erasure gate electrode, and including a portion located between said memory cells and having a thinner thickness than that of a remaining portion of said isolation layer.

A non-volatile semiconductor memory device including a plurality of memory cells, each of said memory cells having a floating gate electrode, an erasure gate electrode stacked on said floating gate electrode and holding a predetermined potential upon injection of charge into said floating gate electrode and an isolation layer controlled by the erasure gate electrode and having a thinner thickness at a portion beneath said erasure gate and at a side edge portion of a channel than that of a remaining portion of said isolation layer, which is fabricated through a process comprising:

• a first step of forming a floating gate electrode on a substrate;
• a second step of providing an isolation layer having a portion thinner in thickness than a remaining portion and located at the side edge portion of a channel, with said floating gate as a mask;
• and
• a third step of stacking an erasure electrode which is held at a grounding potential upon injection of a charge into said floating gate, on said floating gate electrode and said isolation layer.