Method for reducing contact resistance
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsSo Wen Kuo, Chia-Shiung Tsai
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Abstract
A method for substantially improving the electrical characteristics of contact surfaces in contact holes and via holes that are formed in semiconductor substrates is disclosed. The method involves, in particular, the introduction of an "after-etch" process, subsequent to the application of prior art methods of "main-etch," "over-etch," and "soft-etch" that are employed in opening holes in semiconductors, in general. The said process uses an isotropic dry etch assisted by argon gas ions in such a way that the area of the contact surfaces are increased manyfold through the formation of three-dimensional structures. It is shown that the resulting electrical contact resistance of the surfaces is reduced, and therefore, improved substantially.
Claims52
A method of forming an electrically enhanced contact surface in a contact hole on a semiconductor substrate comprising the steps of:
- providing a silicon substrate over which is formed a blanket oxide layer overlying regions including FET devices therein;
- performing a main-etch of said oxide layer through patterned photo-resist mask deposited on the oxidelayer to form contact holes;
- performing an over-etch of said oxide layer through said mask;
- performing soft-etch of exposed silicon in said contact holes through said mask;
- performing after-etch of said silicon through said mask thereby increasing the surface area of said silicon;
- and
- depositing metal in said holes to form contact-plugs.
A method of forming an electrically enhanced contact surface in a contact hole on a semiconductor substrate comprising the steps of:
- providing a silicon substrate over which is formed a blanket oxide layer overlying regions including bipolar devices therein;
- performing a main-etch of said oxide layer through patterned photo-resist mask deposited on the oxidelayer to form contact holes;
- performing an over-etch of said oxide layer through said mask;
- performing soft-etch of exposed silicon in said contact holes through said mask;
- performing after-etch of said silicon through said mask thereby increasing the surface area of said silicon;
- and
- depositing metal in said holes to form contact-plugs.
A method for fabricating a submicron semiconductor integrated IC device comprising:
- forming individual semiconductor devices within and on a semiconductor substrate;
- and forming a multilayer metallurgy structure over and connected to said devices to produce said IC semiconductor device;
- forming a photo-resist mask on a silicon dioxide layer already deposited over said devices;
- performing main-etch, over-etch, soft-etch on said oxide layer to form contact holes followed by after-etch where the soft-etch is performed on exposed silicon, and the after-etch increases the surface area of said silicon;
- depositing metal into said holes to form contact-plugs;
- further depositing metal to form interconnect layer;
- covering said metal layer with interlevel dielectric and then etching through the dielectric over a mask to form via holes;
- further depositing metal in said via holes to form via-plugs;
- further depositing metal to form another interconnect layer.
Dependencies are inferred from the claim text.