Semiconductor chip reclamation technique involving multiple planarization processes

Abstract

A method for removing conductive metals on a semiconductor chip while leaving a foundation on which the conductive metal is in contact with substantially intact. The foundation includes a dielectric layer and a connecting stud. The dielectric layer is formed from a material which has a relatively high reactivity to an attack by a base, but has a relatively low reactivity to an attack by acid. A first planarization process is applied to the semiconductor chip, the first planarization process attacks the conductive metal at a high rate and is discontinued prior to when the connecting stud via is exposed to direct effects of the first planarization process. A second planarization process is applied to the semiconductor chip. The second planarization process attacks the conductive metal at a relatively high rate, but attacks the connecting stud at a low rate. The second planarization process substantially removes what is left of the conductive metal after the first planarization process. A sacrificial material is deposited over the semiconductor chip, the sacrificial material has an etch rate equal to, or higher than, the etch rate of the inter-level dielectric base.

Dependencies are inferred from the claim text.