Low-voltage gate trigger SCR (LVGTSCR) ESD protection circuit for input and output pads

A protection circuit, located on a wire between an internal circuit and a pad, for preventing the internal circuit from damage due to electrostatic discharge, through the pad, comprising:

• a reference high potential;
• a reference low potential;
• a first low-voltage gate trigger silicon controlled
• rectifier, having a first low-voltage gate trigger silicon controlled rectifier anode, a first low-voltage gate trigger silicon controlled rectifier anode gate, a first low-voltage gate trigger silicon controlled rectifier cathode, a first low-voltage gate trigger silicon controlled rectifier cathode gate, and a first low-voltage gate trigger silicon controlled rectifier trigger gate, for protecting the internal circuit against the effect of a negative drain mode and a negative source mode of electrostatic discharge;
• a second low-voltage gate trigger silicon controlled rectifier, having a second low-voltage gate trigger silicon controlled rectifier, anode, a second low-voltage gate trigger silicon controlled rectifier anode gate, a second low-voltage gate trigger silicon controlled rectifier cathode, a second low-voltage gate trigger silicon controlled rectifier cathode gate, and a second low-voltage gate trigger silicon controlled rectifier trigger gate, for protecting the internal circuit against the effect of a positive source mode and a positive drain mode of electrostatic discharge;
• and
• a current-limiting resistor for protection against unexpected electrostatic discharge,
• wherein,
• the first low-voltage gate trigger silicon controlled rectifier anode, the first low-voltage gate trigger silicon controlled rectifier anode gate and the second low-voltage gate trigger silicon controlled rectifier anode gate are each coupled to said reference high potential,
• the first low-voltage gate trigger silicon controlled rectifier cathode gate and the second low-voltage gate trigger silicon controlled rectifier cathode and the second low-voltage gate trigger silicon controlled rectifier cathode gate are each coupled to said reference low potential,
• the first low-voltage gate trigger silicon controlled rectifier cathode and the second low-voltage gate trigger silicon controlled rectifier anode are each coupled to said wire, and
• said current-limiting resistor is connected between the pad and a linked terminal of a trigger gates of said first low-voltage gate trigger silicon controlled rectifier and a linked terminal of trigger gates of said second low-voltage gate trigger silicon controlled rectifier.

A method for preventing a semiconductor circuit from damage due to electrostatic discharge through a semiconductor pad comprising the steps of:

• coupling to a reference high potential a first low-voltage gate trigger silicon controlled rectifier anode, a first low-voltage gate trigger silicon controlled rectifier anode gate, a second low-voltage gate trigger silicon controlled rectifier anode gate and a third low-voltage gate trigger silicon controlled rectifier anode gate;
• coupling to a reference low potential a second low-voltage gate trigger silicon controlled rectifier cathode, a second low-voltage gate trigger silicon controlled rectifier cathode gate and a third low-voltage gate trigger silicon controlled rectifier anode;
• coupling to a wire connected between said semiconductor pad and said semiconductor circuit a first low-voltage gate trigger silicon controlled rectifier cathode, a second low-voltage gate trigger silicon controlled rectifier anode and a third low-voltage gate trigger silicon controlled rectifier cathode;
• and
• connecting a current-limiting resistor between the pad and a linked terminal of trigger gates of said first low-voltage gate trigger silicon controlled rectifier, a linked terminal of trigger gates of said second low-voltage gate trigger silicon controlled rectifier and a linked terminal of trigger gates of said third low-voltage gate trigger silicon controlled rectifier.