Method of manufacturing a microelectronic interlayer dielectric structure

A method for manufacturing a microelectronic device having multiple conductive layers separated by a complex dielectric structure, comprising the steps of:

• a) depositing a first conductive layer on said microelectronic device, wherein said step of depositing comprises sputtering a conductive material to a thickness greater than approximately 0.3 .mu.m;
• b) patterning said first conductive layer to form a plurality of individual conductive lines;
• c) forming a first dielectric layer over said conductive lines by a first film growth process, wherein said first film growth process comprises the steps of reacting, in a plasma vapor phase reaction, Si(OC.sub.2 H.sub.5).sub.4 and O.sub.2 at a temperature in the range of approximately 300.degree. C. to approximately 500.degree. C., at a pressure in the range of approximately 2 torr to 20 torr, and at an RF power in the range of approximately 100 W to approximately 1,000 W, such that said first dielectric layer has compression stress;
• d) forming a second dielectric layer, on top of said first dielectric layer, by a second film growth process, wherein said second film growth process comprises the steps of reacting, Si(OC.sub.2 H.sub.5).sub.4 and O.sub.3 /O.sub.2 at a temperature in the range of approximately 300.degree. C. to approximately 500.degree. C., at a pressure in the range of approximately 10 torr to approximately 760 torr, and using an inert carrier gas, such that said second dielectric layer has tensile stress;
• e) etching said second dielectric layer to expose a portion of said first dielectric layer;
• f) forming a layer of spin-on-glass over the surface of said first and second dielectric layers;
• g) etching said spin-on-glass layer until the surface has been planarized;
• h) forming a third dielectric layer, above said second dielectric layer, by said first film growth process;
• i) etching contact holes through said third and first dielectric layers;
• and
• j) depositing a second conductive layer on the surface comprising said third dielectric layer and said contact holes.