Polishstop planarization structure
AssigneeInternational Business Machines Corporation
InventorsPeter A. Burke, Michael A. Leach
Life of this patent
Estimating the term…
Abstract
The invention provides a method for producing a substantially planar surface overlying features of a semiconductor structure. The method comprises forming alternating layers of a hard polishing material and a soft polishing material over the features of the semiconductor structure, and then polishing the alternating layers to form a substantially planar surface over the features. The method takes advantage of the polish rates of the various materials used as alternating layers to enhance the planarization process.
Claims7
A semiconductor device having a substantially planar top surface thereof, said device comprising:
- a substrate having a top surface thereof;
- raised features positioned on said top surface of said substrate;
- one or more filled vias extending upward from said raised features, each of said filled vias having a top surface thereof;
- a first layer of a soft polishing material overlying said top surface of said substrate and surrounding said one or more filled vias;
- a second layer of a hard polishing material overlying said first layer of a soft polishing material;
- a third layer of a soft polishing material overlying said second layer of a hard polishing material;
- and
- a conformal fourth layer of a hard polishing material overlying said third layer of a soft polishing material,
- wherein portions of said fourth layer of a hard polishing material, portions of said third layer of a soft polishing material, and said top surfaces of each of said one or more filled vias comprise said substantially planar surface.
Dependencies are inferred from the claim text.